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公开(公告)号：US10951445B2
公开(公告)日：2021-03-16
申请号：US16191611
申请日：2018-11-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Barosaim Sung , Chilun Lo , Jae-hoon Lee , Jong-woo Lee , Seung-hyun Oh
Abstract: A radio frequency (RF) integrated circuit is provided. The RF integrated circuit supports carrier aggregation and includes first receiving circuits and a first shared phase locked loop circuit that provides a first frequency signal of a first frequency to the first receiving circuits. One of the first receiving circuits includes an analog to digital converter (ADC) and a digital conversion circuit. The ADC converts an RF signal received by the one of the first receiving circuits to a digital signal by using the first frequency signal. The digital conversion circuit generates a digital baseband signal by performing frequency down conversion on the digital signal.
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公开(公告)号：US20190007057A1
公开(公告)日：2019-01-03
申请号：US16104414
申请日：2018-08-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jae-Hoon Lee , Jong-woo Lee , Chilun Lo , Seung-hyun Oh , Jong-mi Lee
IPC: H03M3/00
Abstract: A variable feedback gain delta modulator includes group of capacitors commonly connected to a first terminal and are respectively classified into a first capacitor group and a second capacitor group; a comparator for sequentially generating n-bit digital output signals based on a voltage of the first terminal; and a switch group including switches respectively connected to the capacitors, wherein the switches are respectively classified into a first switch group and a second switch group respectively connected to the first capacitor group and the second capacitor group, and the first switch group and the second switch group respectively operate according to a first control signal and a second control signal that are determined based on the n-bit digital output signals and the variable feedback gain.
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公开(公告)号：US20200177213A1
公开(公告)日：2020-06-04
申请号：US16779763
申请日：2020-02-03
Applicant: SAMSUNG ELECTRONICS CO,, LTD.
Inventor： SEUNG-HYUN OH , Chilun Lo , Barosaim Sung , Jae-hoon Lee , Jong-woo Lee
Abstract: Provided are a radio-frequency integrated chip (RFIC) and a wireless communication device including the RFIC. An RFIC configured to receive a carrier aggregated receive signal having at least first and second carrier signals may include first and second carrier receivers configured to generate, from the receive signal, first and second digital carrier signals, respectively. A phase-locked loop (PLL) may output a first frequency signal having a first frequency to the first carrier receiver and the second carrier receiver. The first and second carrier receivers may include first and second analog mixers, respectively, for translating frequencies of the receive signal, using the first frequency signal and the second frequency signal, respectively. Each of the first and second carrier receivers may further include a digital mixer for further translating the frequencies of the receive signal in the digital domain.
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公开(公告)号：US10110248B2
公开(公告)日：2018-10-23
申请号：US15702962
申请日：2017-09-13
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jae-hoon Lee , Jong-woo Lee , Chilun Lo , Seung-hyun Oh , Jong-mi Lee
IPC: H03M3/00
Abstract: A variable feedback gain delta modulator includes group of capacitors commonly connected to a first terminal and are respectively classified into a first capacitor group and a second capacitor group; a comparator for sequentially generating n-bit digital output signals based on a voltage of the first terminal; and a switch group including switches respectively connected to the capacitors, wherein the switches are respectively classified into a first switch group and a second switch group respectively connected to the first capacitor group and the second capacitor group, and the first switch group and the second switch group respectively operate according to a first control signal and a second control signal that are determined based on the n-bit digital output signals and the variable feedback gain.
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Patent Agency Ranking
公开(公告)号：US11611315B2
公开(公告)日：2023-03-21
申请号：US17173943
申请日：2021-02-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jong Mi Lee , Yong Lim , Chilun Lo
Abstract: A noise filtering circuit including: an amplifier which receives a reference bias through a first input terminal, generates an amplified output voltage and outputs the amplified output voltage through an output terminal, and receives an output voltage generated on the basis of the amplified output voltage through a second input terminal; a resistance component connected between the output terminal of the amplifier and the second input terminal; and a capacitor connected to the resistance component.
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公开(公告)号：US11031962B2
公开(公告)日：2021-06-08
申请号：US16779763
申请日：2020-02-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seung-hyun Oh , Chilun Lo , Barosaim Sung , Jae-hoon Lee , Jong-woo Lee
Abstract: Provided are a radio-frequency integrated chip (RFIC) and a wireless communication device including the RFIC. An RFIC configured to receive a carrier aggregated receive signal having at least first and second carrier signals may include first and second carrier receivers configured to generate, from the receive signal, first and second digital carrier signals, respectively. A phase-locked loop (PLL) may output a first frequency signal having a first frequency to the first carrier receiver and the second carrier receiver. The first and second carrier receivers may include first and second analog mixers, respectively, for translating frequencies of the receive signal, using the first frequency signal and the second frequency signal, respectively. Each of the first and second carrier receivers may further include a digital mixer for further translating the frequencies of the receive signal in the digital domain.
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公开(公告)号：US10560128B2
公开(公告)日：2020-02-11
申请号：US16203943
申请日：2018-11-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seung-hyun Oh , Chilun Lo , Barosaim Sung , Jae-hoon Lee , Jong-woo Lee
Abstract: Provided are a radio-frequency integrated chip (RFIC) and a wireless communication device including the RFIC. An RFIC configured to receive a carrier aggregated receive signal having at least first and second carrier signals may include first and second carrier receivers configured to generate, from the receive signal, first and second digital carrier signals, respectively. A phase-locked loop (PLL) may output a first frequency signal having a first frequency to the first carrier receiver and the second carrier receiver. The first and second carrier receivers may include first and second analog mixers, respectively, for translating frequencies of the receive signal, using the first frequency signal and the second frequency signal, respectively. Each of the first and second carrier receivers may further include a digital mixer for farther translating the frequencies of the receive signal in the digital domain.
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公开(公告)号：US10439636B2
公开(公告)日：2019-10-08
申请号：US16104414
申请日：2018-08-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jae-Hoon Lee , Jong-woo Lee , Chilun Lo , Seung-hyun Oh , Jong-mi Lee
IPC: H03M3/00
Abstract: A variable feedback gain delta modulator includes group of capacitors commonly connected to a first terminal and are respectively classified into a first capacitor group and a second capacitor group; a comparator for sequentially generating n-bit digital output signals based on a voltage of the first terminal; and a switch group including switches respectively connected to the capacitors, wherein the switches are respectively classified into a first switch group and a second switch group respectively connected to the first capacitor group and the second capacitor group, and the first switch group and the second switch group respectively operate according to a first control signal and a second control signal that are determined based on the n-bit digital output signals and the variable feedback gain.
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公开(公告)号：US20190173501A1
公开(公告)日：2019-06-06
申请号：US16203943
申请日：2018-11-29
Applicant: Samsung Electronics Co., LTD.
Inventor： SEUNG-HYUN OH , Chilun Lo , Barosaim Sung , Jae-Hoon Lee , Jong-Woo Lee
Abstract: Provided are a radio-frequency integrated chip (RFIC) and a wireless communication device including the RFIC. An RFIC configured to receive a carrier aggregated receive signal having at least first and second carrier signals may include first and second carrier receivers configured to generate, from the receive signal, first and second digital carrier signals, respectively. A phase-locked loop (PLL) may output a first frequency signal having a first frequency to the first carrier receiver and the second carrier receiver. The first and second carrier receivers may include first and second analog mixers, respectively, for translating frequencies of the receive signal, using the first frequency signal and the second frequency signal, respectively, Each of the first and second carrier receivers may further include a digital mixer for farther translating the frequencies of the receive signal in the digital domain.
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