利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

56 条记录 (耗时 0.016 秒)

    Randomly sampling reference ADC for calibration
    1.
    发明授权
    Randomly sampling reference ADC for calibration 有权
    随机采样参考ADC进行校准

    公开(公告)号：US09525428B2

    公开(公告)日：2016-12-20

    申请号：US14955905

    申请日：2015-12-01

    申请人： ANALOG DEVICES, INC.

    发明人： Siddharth Devarajan ,  Eric Otte ,  Nevena Rakuljic ,  Carroll C. Speir

    IPC分类号： H03M1/12 ,  H03M1/10 ,  H03M1/46 ,  H03M3/00

    CPC分类号： H03M1/128 ,  H03M1/1019 ,  H03M1/1028 ,  H03M1/12 ,  H03M1/121 ,  H03M1/1215 ,  H03M1/46 ,  H03M1/462 ,  H03M1/468 ,  H03M3/382 ,  H03M3/498

    摘要： Analog-to-digital converters (ADCs) can have errors which can affect their performance. To improve the performance, many techniques have been used to compensate or correct for the errors. When the ADCs are being implemented with sub-micron technology, ADCs can be readily and easily equipped with an on-chip microprocessor for performing a variety of digital functions. The on-chip microprocessor and any suitable digital circuitry can implement functions for reducing those errors, enabling certain undesirable artifacts to be reduced, and providing a flexible platform for a highly configurable ADC. The on-chip microprocessor is particularly useful for a randomized time-interleaved ADC. Moreover, a randomly sampling ADC can be added in parallel to a main ADC for calibration purposes. Furthermore, the overall system can include an efficient implementation for correcting errors in an ADC.

    摘要翻译： 模数转换器（ADC）可能会产生可能影响其性能的错误。 为了提高性能，已经使用许多技术来补偿或纠正错误。 当ADC采用亚微米技术实现时，ADC可以轻松轻松配备一个片上微处理器，用于执行各种数字功能。 片上微处理器和任何合适的数字电路可以实现减少这些错误的功能，从而能够减少某些不必要的伪像，并为高度可配置的ADC提供灵活的平台。 片上微处理器对于随机时间交织ADC特别有用。 此外，随机采样ADC可以并行添加到主ADC用于校准目的。 此外，整个系统可以包括用于校正ADC中的错误的有效实现。

    Sigma-delta modulator and method thereof
    2.
    发明授权
    Sigma-delta modulator and method thereof 有权
    Sigma-delta调制器及其方法

    公开(公告)号：US07916055B2

    公开(公告)日：2011-03-29

    申请号：US12468049

    申请日：2009-05-18

    申请人： Kuo-Hsin Chen

    发明人： Kuo-Hsin Chen

    IPC分类号： H03M3/00

    CPC分类号： H03M3/498

    摘要： A sigma-delta modulator includes an adder, a filter, a quantizer, and a clock rate controller. The adder receives an input signal and an output signal to generate a summation signal. The filter is coupled to the adder and filters the summation signal to generate a filtered signal. The quantizer is coupled to the filter as well as the adder and quantizes the filtered signal to generate the output signal according to a first clock signal. The clock rate controller is coupled to the quantizer and generates the first clock signal, wherein a frequency of the first clock signal is variable.

    摘要翻译： Σ-Δ调制器包括加法器，滤波器，量化器和时钟速率控制器。 加法器接收输入信号和输出信号以产生求和信号。 滤波器耦合到加法器并对求和信号进行滤波以产生滤波信号。 量化器耦合到滤波器以及加法器，并对滤波信号进行量化，以根据第一时钟信号产生输出信号。 时钟速率控制器耦合到量化器并产生第一时钟信号，其中第一时钟信号的频率是可变的。

    IMPLANTABLE MEDICAL DEVICE WITH ADJUSTABLE SIGMA-DELTA ANALOG-TO-DIGITAL CONVERSION CLOCK RATE
    3.
    发明申请
    IMPLANTABLE MEDICAL DEVICE WITH ADJUSTABLE SIGMA-DELTA ANALOG-TO-DIGITAL CONVERSION CLOCK RATE 有权
    具有可调整SIGMA-DELTA模拟数字转换时钟速率的可植入医疗设备

    公开(公告)号：US20080079617A1

    公开(公告)日：2008-04-03

    申请号：US11536942

    申请日：2006-09-29

    申请人： Mark A. Frigaard ,  Michael W. Heinks ,  Joel A. Anderson ,  Robert H. Mehregan

    发明人： Mark A. Frigaard ,  Michael W. Heinks ,  Joel A. Anderson ,  Robert H. Mehregan

    IPC分类号： H03M1/66

    CPC分类号： H03M3/32 ,  A61N1/3704 ,  H03M3/498

    摘要： An implantable medical device, such as a pacemaker or implantable cardioverter defibrillator, uses digital signal processing channels to process sensed time varying signals representing cardiac activity. Each digital signal processing channels includes a sigma-Delta analog-to-digital converter. The clock rate of each sigma-delta analog-to-digital converter is controlled as a function of a signal detection threshold for its respective digital signal processing channel. For higher threshold levels, a reduced clock rate for the sigma-delta analog-to-digital converter results in reduced power consumption and longer battery life.

    摘要翻译： 可植入医疗装置，例如起搏器或植入式心律转复除颤器，使用数字信号处理通道来处理表示心脏活动的感测时变信号。 每个数字信号处理通道包括一个Σ-Δ模数转换器。 每个Σ-Δ模数转换器的时钟速率被控制为其相应的数字信号处理通道的信号检测阈值的函数。 对于更高的阈值电平，Σ-Δ模数转换器的降低的时钟频率导致功耗降低并延长电池寿命。

    A/D conversion circuit with carrier frequency removing feature
    6.
    发明申请
    A/D conversion circuit with carrier frequency removing feature 失效
    具有载波频率去除功能的A / D转换电路

    公开(公告)号：US20070057833A1

    公开(公告)日：2007-03-15

    申请号：US11507801

    申请日：2006-08-22

    申请人： Shinichi Amemiya

    发明人： Shinichi Amemiya

    IPC分类号： H03M1/12

    CPC分类号： H03M3/41 ,  H03M3/424 ,  H03M3/498

    摘要： The present invention is intended to fully remove a carrier-frequency component despite a compact low-cost configuration. An A/D conversion circuit with a carrier frequency removing feature includes: an A/D converter including a voltage comparator that compares a first signal with a feedback signal and a voltage feedback circuit that produces the feedback signal; a one-input N-output demultiplexer that receives the feedback signal; N integrators that calculate the respective integrals of N output signals of the demultiplexer; an N-input one-output multiplexer that receives the outputs of the N respective integrators; a subtractor that produces a difference between an analog signal and the output signal of the multiplexer; an amplifier that amplifies the output signal of the subtractor to produce the first signal; and a switching control circuit that cyclically switches the input terminals of the multiplexer and the output terminals of the demultiplexer synchronously with a carrier wave.

    摘要翻译： 尽管紧凑的低成本配置，本发明旨在完全去除载波频率分量。 具有载波频率去除功能的A / D转换电路包括：A / D转换器，其包括将第一信号与反馈信号进行比较的电压比较器和产生反馈信号的电压反馈电路; 接收反馈信号的单输入N输出解复用器; N个积分器，其计算解复用器的N个输出信号的各自积分; N输入单输出多路复用器，其接收N个相应积分器的输出; 减法器，其产生模拟信号和多路复用器的输出信号之间的差异; 放大器，放大减法器的输出信号以产生第一信号; 以及切换控制电路，其与载波同步地循环地切换多路复用器的输入端和解复用器的输出端。

    Delta sigma type AD converter
    7.
    发明申请
    Delta sigma type AD converter 失效
    Δ西格玛型AD转换器

    公开(公告)号：US20020171572A1

    公开(公告)日：2002-11-21

    申请号：US10141081

    申请日：2002-05-09

    申请人： Pioneer Corporation

    发明人： Yuji Yamamoto

    IPC分类号： H03M003/00

    CPC分类号： H03M3/498 ,  H03M3/406 ,  H03M3/454

    摘要： On a first stage of the delta sigma type AD converter for quantizing an input analog signal and converting it to an output digital signal. The computing element adds a feedback signal from a second stage DA converter and subtracts a feedback signal in which the output of the delay unit is multiplied at a coefficient null with a coefficient buffer and a feedback signal from the delay unit, the input analog signal is output to a computing element on a post stage, and quantization is executed with a predetermined sampling frequency by a quantizing element so as to convert it to an output digital signal. The frequency characteristic of quantization noise Q(Z) to be added by the quantizing element can be adjusted with the coefficient null, so that the relationship between the sampling frequency and the input frequency can be set up appropriately.

    摘要翻译： 在用于量化输入模拟信号并将其转换为输出数字信号的Δ-Σ型AD转换器的第一级上。 计算单元加上来自第二级DA转换器的反馈信号，并减去延迟单元的输出以系数α与系数缓冲器和来自延迟单元的反馈信号相乘的反馈信号，输入模拟信号为 输出到后级的计算元件，并且通过量化元件以预定的采样频率执行量化，以便将其转换为输出数字信号。 可以用系数α来调整由量化元件添加的量化噪声Q（Z）的频率特性，从而可以适当地设定采样频率与输入频率之间的关系。

    Analog to digital conversion using non-uniform sample rates
    8.
    发明授权
    Analog to digital conversion using non-uniform sample rates 失效
    使用不均匀采样率的模数转换

    公开(公告)号：US5485152A

    公开(公告)日：1996-01-16

    申请号：US328560

    申请日：1994-10-25

    申请人： James Wilson ,  Ronald A. Cellini ,  James M. Sobol

    发明人： James Wilson ,  Ronald A. Cellini ,  James M. Sobol

    IPC分类号： H03M1/00 ,  H03H17/00 ,  H03H17/06 ,  H03L7/08 ,  H03L7/093 ,  H03L7/099 ,  H03M1/12 ,  H03M3/02 ,  H03M3/04 ,  H03M7/36

    CPC分类号： H03H17/06 ,  H03H17/0614 ,  H03H17/0628 ,  H03L7/08 ,  H03L7/093 ,  H03L7/0992 ,  H03M3/498 ,  H03L2207/50

    摘要： A method and apparatus for analog to digital conversion using sigma-delta modulation of the temporal spacing between digital samples. The method and apparatus of the present invention provides for sigma-delta modulation of the time base such that errors produced by non-uniform sampling are frequency-shaped to a region (i.e., shifted to higher frequencies) where they can be removed by conventional filtering techniques. In one embodiment, digital data is interpolated under control of a sigma-delta modulated frequency selection signal that represents, on average, the data rate of the digital data to be output by the converter and then decimated by a fixed ratio. The frequency selection signal is modulated using an n-th order m-bit sigma-delta modulator. Data thus emerges from the interpolation/decimation process at the sample rate selected by the n-th order m-bit sigma-delta modulator. The method and apparatus converts the data rate of an incoming digital data stream from an ADC to the data rate determined by the n-th order m-bit sigma-delta modulator.

    摘要翻译： 一种使用数字样本之间的时间间隔的Σ-Δ调制进行模数转换的方法和装置。 本发明的方法和装置提供了时基的Σ-Δ调制，使得由非均匀采样产生的误差是频率形状的区域（即，转移到更高的频率），其中它们可以通过常规滤波被去除 技术 在一个实施例中，在Σ-Δ调制频率选择信号的控制下内插数字数据，该Δ-Δ调制频率选择信号平均表示要由转换器输出的数字数据的数据速率，然后以固定比率被抽取。 使用第n级m位Σ-Δ调制器调制频率选择信号。 数据因此从由第n级m比特Σ-Δ调制器选择的采样率的内插/抽取处理中出现。 该方法和装置将来自ADC的输入数字数据流的数据速率转换为由第n位m位Σ-Δ调制器确定的数据速率。