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公开(公告)号：US11587977B2
公开(公告)日：2023-02-21
申请号：US17173865
申请日：2021-02-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dong-Jun Seong , Soon-Oh Park
Abstract: A method of manufacturing a memory device includes sequentially forming and then etching a preliminary selection device layer, a preliminary middle electrode layer, and a preliminary variable resistance layer on a substrate, thereby forming a selection device, a middle electrode, and a variable resistance layer. At least one of a side portion of the selection device or a side portion of the variable resistance layer is removed so that a first width of the middle electrode in a first direction parallel to a top of the substrate is greater than a second width of the variable resistance layer in the first direction or a third width of the selection device in the first direction. A capping layer is formed on at least one of a side wall of the etched side portion of the selection device or a side wall of the etched side portion of the variable resistance layer.
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公开(公告)号：US10957740B2
公开(公告)日：2021-03-23
申请号：US16447370
申请日：2019-06-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dong-Jun Seong , Soon-Oh Park
Abstract: A method of manufacturing a memory device includes sequentially forming and then etching a preliminary selection device layer, a preliminary middle electrode layer, and a preliminary variable resistance layer on a substrate, thereby forming a selection device, a middle electrode, and a variable resistance layer. At least one of a side portion of the selection device or a side portion of the variable resistance layer is removed so that a first width of the middle electrode in a first direction parallel to a top of the substrate is greater than a second width of the variable resistance layer in the first direction or a third width of the selection device in the first direction. A capping layer is formed on at least one of a side wall of the etched side portion of the selection device or a side wall of the etched side portion of the variable resistance layer.
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公开(公告)号：US11227991B2
公开(公告)日：2022-01-18
申请号：US16916227
申请日：2020-06-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dong-Jun Seong , Sung-Ho Eun , Soon-Oh Park
Abstract: A semiconductor memory device includes first conductive lines extending in a first direction on a substrate, second conductive lines extending in a second direction over the first conductive line, the first and the second conductive lines crossing each other at cross points, a cell structure positioned at each of the cross points, each of the cell structures having a data storage element, a selection element to apply a cell selection signal to the data storage element and to change a data state of the data storage element, and an electrode element having at least an electrode with a contact area smaller than that of the selection element, and an insulation pattern insulating the first and the second conductive lines and the cell structures from one another.
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Patent Agency Ranking
公开(公告)号：US20200066799A1
公开(公告)日：2020-02-27
申请号：US16359146
申请日：2019-03-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dong-Jun Seong , Yong-Jin Park , Jun-Hwan Paik , Gyu-Hwan Oh
Abstract: A variable resistance memory device may include a first conductive line, a plurality of stacked structures, and a mold pattern. The first conductive line may be formed on a substrate. The plurality of stacked structures may be formed on the first conductive line, and each of the plurality of stacked structures includes a lower electrode, a variable resistance pattern, and a middle electrode stacked on one another. The mold pattern may be formed on the first conductive line to fill a space between the plurality of stacked structures. An upper portion of the mold pattern may include a surface treated layer and a lower portion of the mold pattern may include a non-surface treated layer.
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公开(公告)号：US10374008B2
公开(公告)日：2019-08-06
申请号：US15655118
申请日：2017-07-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dong-Jun Seong , Soon-Oh Park
IPC: H01L27/24
Abstract: A method of manufacturing a memory device includes sequentially forming and then etching a preliminary selection device layer, a preliminary middle electrode layer, and a preliminary variable resistance layer on a substrate, thereby forming a selection device, a middle electrode, and a variable resistance layer. At least one of a side portion of the selection device or a side portion of the variable resistance layer is removed so that a first width of the middle electrode in a first direction parallel to a top of the substrate is greater than a second width of the variable resistance layer in the first direction or a third width of the selection device in the first direction. A capping layer is formed on at least one of a side wall of the etched side portion of the selection device or a side wall of the etched side portion of the variable resistance layer.
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公开(公告)号：US11770938B2
公开(公告)日：2023-09-26
申请号：US17592087
申请日：2022-02-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dong-Jun Seong , Soon-Oh Park
CPC classification number: H10B63/24 , H10B63/84 , H10B63/845 , H10N70/063 , H10N70/231 , H10N70/826 , H10N70/828 , H10N70/8828
Abstract: A method of manufacturing a memory device includes sequentially forming and then etching a preliminary selection device layer, a preliminary middle electrode layer, and a preliminary variable resistance layer on a substrate, thereby forming a selection device, a middle electrode, and a variable resistance layer. At least one of a side portion of the selection device or a side portion of the variable resistance layer is removed so that a first width of the middle electrode in a first direction parallel to a top of the substrate is greater than a second width of the variable resistance layer in the first direction or a third width of the selection device in the first direction. A capping layer is formed on at least one of a side wall of the etched side portion of the selection device or a side wall of the etched side portion of the variable resistance layer.
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公开(公告)号：US10692933B2
公开(公告)日：2020-06-23
申请号：US16359146
申请日：2019-03-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dong-Jun Seong , Yong-Jin Park , Jun-Hwan Paik , Gyu-Hwan Oh
Abstract: A variable resistance memory device may include a first conductive line, a plurality of stacked structures, and a mold pattern. The first conductive line may be formed on a substrate. The plurality of stacked structures may be formed on the first conductive line, and each of the plurality of stacked structures includes a lower electrode, a variable resistance pattern, and a middle electrode stacked on one another. The mold pattern may be formed on the first conductive line to fill a space between the plurality of stacked structures. An upper portion of the mold pattern may include a surface treated layer and a lower portion of the mold pattern may include a non-surface treated layer.
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公开(公告)号：US09780144B2
公开(公告)日：2017-10-03
申请号：US15342497
申请日：2016-11-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dong-Jun Seong , Soon-Oh Park
IPC: H01L27/24
CPC classification number: H01L27/2427 , H01L27/2481 , H01L27/249 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/144 , H01L45/1675
Abstract: A method of manufacturing a memory device includes sequentially forming and then etching a preliminary selection device layer, a preliminary middle electrode layer, and a preliminary variable resistance layer on a substrate, thereby forming a selection device, a middle electrode, and a variable resistance layer. At least one of a side portion of the selection device or a side portion of the variable resistance layer is removed so that a first width of the middle electrode in a first direction parallel to a top of the substrate is greater than a second width of the variable resistance layer in the first direction or a third width of the selection device in the first direction. A capping layer is formed on at least one of a side wall of the etched side portion of the selection device or a side wall of the etched side portion of the variable resistance layer.
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