公开(公告)号：US20190266114A1

公开(公告)日：2019-08-29

申请号：US16411330

申请日：2019-05-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HAN-JU LEE ,  YOUNGKWANG YOO ,  YOUNGJIN CHO

IPC: G06F13/16 ,  G06F13/40

Abstract: A storage device includes random access memories, nonvolatile memory devices, a controller configured to control the nonvolatile memory devices, and a driver circuit configured to receive a command and an address from an external device, output a buffer command according to the command and the address, and transmit the command and the address to one of a first channel connected to the random access devices and a second channel connected to the controller according to the command and the address. The storage device further includes a plurality of data buffers configured to communicate with the external device and electrically connect the external device to one of a third channel connected to the random access memory devices and a fourth channel connected to the controller in response to the buffer command. Each of the data buffers includes a FIFO (first-in first-out) circuit.

公开(公告)号：US20170075829A1

公开(公告)日：2017-03-16

申请号：US15260916

申请日：2016-09-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HAN-JU LEE ,  YOUNGKWANG YOO ,  YOUNGJIN CHO

IPC: G06F13/16 ,  G06F13/40

CPC classification number: G06F13/1673 ,  G06F13/4072

Abstract: A storage device includes random access memories, nonvolatile memory devices, a controller configured to control the nonvolatile memory devices, and a driver circuit configured to receive a command and an address from an external device, output a buffer command according to the command and the address, and transmit the command and the address to one of a first channel connected to the random access devices and a second channel connected to the controller according to the command and the address. The storage device further includes a plurality of data buffers configured to communicate with the external device and electrically connect the external device to one of a third channel connected to the random access memory devices and a fourth channel connected to the controller in response to the buffer command. Each of the data buffers includes a FIFO (first-in first-out) circuit.

Abstract translation: 存储装置包括随机存取存储器，非易失性存储器件，被配置为控制非易失性存储器件的控制器和被配置为从外部设备接收命令和地址的驱动器电路，根据命令和地址输出缓冲器命令 并且将命令和地址发送到连接到随机接入设备的第一信道中的一个，以及根据命令和地址连接到控制器的第二信道。 存储设备还包括多个数据缓冲器，其被配置为与外部设备进行通信，并且将外部设备电连接到连接到随机存取存储器设备的第三通道中的一个和响应于缓冲器命令连接到控制器的第四通道 。 每个数据缓冲器包括FIFO（先入先出）电路。

公开(公告)号：US20190354474A1

公开(公告)日：2019-11-21

申请号：US16195533

申请日：2018-11-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HAN-JU LEE ,  YOUNGJIN CHO ,  SUNGYONG SEO ,  YOUNGKWANG YOO

IPC: G06F12/02 ,  G06F3/06 ,  G06F13/16 ,  G06F13/42 ,  G06F12/06

Abstract: The nonvolatile memory module includes at least one nonvolatile memory device and a device controller configured to receive a storage command from an external device and to perform an operation corresponding to the received storage command The device controller includes a random access memory (RAM). After completing the corresponding operation, the device controller stores status information in the RAM and then transmits an alert signal to the external device.

公开(公告)号：US20190205037A1

公开(公告)日：2019-07-04

申请号：US16298318

申请日：2019-03-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HAN-JU LEE ,  YOUNGKWANG YOO ,  YOUNGJIN CHO

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0688 ,  G06F13/385

Abstract: A storage device includes a data buffer, a device controller, and nonvolatile memories. The data buffer is configured to transact data from an external device. The device controller is configured to receive a command and an address from an external device, to control the data buffers, and to transact data with the data buffers. The nonvolatile memories are configured to perform write, read, and erase operations under control of the device controller. When a first link training between an external device and the data buffers is performed by the external device, the device controller performs a second link training between the device controller and a data buffer internally without control of the external device.

公开(公告)号：US20160357665A1

公开(公告)日：2016-12-08

申请号：US15083425

申请日：2016-03-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HAN-JU LEE ,  YOUNGJIN CHO ,  SUNGYONG SEO ,  YOUNGKWANG YOO

IPC: G06F12/02 ,  G06F12/06 ,  G06F13/42

CPC classification number: G06F12/0246 ,  G06F12/0638 ,  G06F13/4282 ,  G06F2212/205 ,  G06F2212/7208

Abstract: The nonvolatile memory module includes at least one nonvolatile memory device and a device controller configured to receive a storage command from an external device and to perform an operation corresponding to the received storage command The device controller includes a random access memory (RAM). After completing the corresponding operation, the device controller stores status information in the RAM and then transmits an alert signal to the external device.

Abstract translation: 非易失性存储器模块包括至少一个非易失性存储器设备和被配置为从外部设备接收存储命令并执行与所接收的存储命令相对应的操作的设备控制器。设备控制器包括随机存取存储器（RAM）。 在完成相应的操作之后，设备控制器将状态信息存储在RAM中，然后向外部设备发送警报信号。

公开(公告)号：US20160357454A1

公开(公告)日：2016-12-08

申请号：US15055689

申请日：2016-02-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： HAN-JU LEE ,  YOUNGKWANG YOO ,  YOUNGJIN CHO

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0688 ,  G06F13/385

Abstract: A storage device includes a data buffer, a device controller, and nonvolatile memories. The data buffer is configured to transact data from an external device. The device controller is configured to receive a command and an address from an external device, to control the data buffers, and to transact data with the data buffers. The nonvolatile memories are configured to perform write, read, and erase operations under control of the device controller. When a first link training between an external device and the data buffers is performed by the external device, the device controller performs a second link training between the device controller and a data buffer internally without control of the external device.

Abstract translation: 存储设备包括数据缓冲器，设备控制器和非易失性存储器。 数据缓冲区配置为从外部设备处理数据。 设备控制器被配置为从外部设备接收命令和地址，以控制数据缓冲器，并与数据缓冲器进行数据交互。 非易失性存储器被配置为在设备控制器的控制下执行写入，读取和擦除操作。 当由外部设备执行外部设备与数据缓冲器之间的第一链路训练时，设备控制器在内部对设备控制器和数据缓冲器之间执行第二链路训练，而无需外部设备的控制。

公开(公告)号：US20150135042A1

公开(公告)日：2015-05-14

申请号：US14541303

申请日：2014-11-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KWANGSEOK IM ,  JUNG-YEON YOON ,  HAN-JU LEE ,  HA-NEUL JEONG

IPC: G06F11/10 ,  H03M13/09

CPC classification number: G06F11/1004 ,  G06F11/1008 ,  G06F11/1076 ,  H03M13/09

Abstract: A memory controller comprises at least one interface configured to receive a request, user data, and an address from an external source, a first data check engine configured to generate data check information based on the received address and the user data in response to the received request, and a second data check engine configured to check the integrity of the user data based on the generated data check information where the user data is transmitted to the nonvolatile memory. The memory controller is configured to transmit the user data received from the external source to an external destination where the integrity of the user data is verified according to a check result, and is further configured to transmit an interrupt signal to the external source and the external destination where the check result indicates that the user data comprises an error.

Abstract translation: 存储器控制器包括被配置为从外部源接收请求，用户数据和地址的至少一个接口，第一数据检查引擎，被配置为基于接收到的地址和用户数据响应于所接收的地址生成数据检查信息 以及第二数据检查引擎，被配置为基于将用户数据发送到非易失性存储器的所生成的数据检查信息来检查用户数据的完整性。 存储器控制器被配置为根据检查结果将从外部源接收的用户数据发送到外部目的地，其中用户数据的完整性被验证，并且还被配置为将中断信号发送到外部源和外部 检查结果指示用户数据包含错误的目的地。