公开(公告)号：US20230185463A1

公开(公告)日：2023-06-15

申请号：US18105920

申请日：2023-02-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNGJIN CHO

IPC: G06F3/06 ,  G06F12/06 ,  G06F12/02

CPC classification number: G06F3/0623 ,  G06F3/0614 ,  G06F3/0632 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F12/0646

Abstract: A storage controller including: a host interface circuit receiving first, second, third and fourth requests corresponding to first, second, third and fourth logical addresses; a memory interface circuit communicating with first nonvolatile memories through a first channel and second nonvolatile memories through a second channel; a first flash translation layer configured to manage the first nonvolatile memories; and a second flash translation layer configured to manage the second nonvolatile memories, the first flash translation layer outputs commands corresponding to the first and fourth requests through the first channel, and the second flash translation layer outputs commands respectively corresponding to the second and third requests through the second channel, and a value of the first logical address is smaller than a value of the second logical address, and a value of the third logical address is smaller than a value of the fourth logical address.

公开(公告)号：US20170075576A1

公开(公告)日：2017-03-16

申请号：US15260932

申请日：2016-09-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNGJIN CHO

IPC: G06F3/06 ,  G11C14/00

CPC classification number: G11C14/0018 ,  G06F11/14 ,  G06F12/00 ,  G06F12/0246 ,  G11C5/04 ,  G11C5/143 ,  G11C7/14 ,  G11C8/16 ,  G11C11/005

Abstract: A memory module includes a nonvolatile memory device and a volatile memory device connected to a first data channel through a first input/output port and to a second data channel through a second input/output port. The volatile memory device activates one of the first and second input/output ports based on an operation mode. The memory module includes a registering clock driver that transmits a first control signal for data exchange through the first input/output port and a second control signal for data exchange through the second input/output port, to the volatile memory device. A memory controller of the memory module generates the second control signal, exchanges data with the volatile memory device through the second data channel, and controls the nonvolatile memory device. The memory controller detects a request from a host or a power status and generates the second control signal based on the detection result.

Abstract translation: 存储器模块包括非易失性存储器件和通过第一输入/输出端口连接到第一数据通道并通过第二输入/输出端口连接到第二数据通道的易失性存储器件。 易失性存储器件基于操作模式激活第一和第二输入/输出端口中的一个。 存储器模块包括寄存时钟驱动器，其通过第一输入/输出端口发送用于数据交换的第一控制信号和用于通过第二输入/输出端口进行数据交换的第二控制信号到易失性存储器件。 存储器模块的存储器控​​制器产生第二控制信号，通过第二数据通道与易失性存储器件交换数据，并且控制非易失性存储器件。 存储器控制器检测来自主机的请求或电源状态，并且基于检测结果生成第二控制信号。

公开(公告)号：US20160364153A1

公开(公告)日：2016-12-15

申请号：US15055779

申请日：2016-02-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HEE HYUN NAM ,  YOUNGJIN CHO

IPC: G06F3/06

CPC classification number: G11C16/00 ,  G06F11/00

Abstract: A storage device includes nonvolatile memories and a device controller configured to store data being received from an external device in an internal RAM, according to a command and an address being received from the external device. The device controller controls the nonvolatile memories according to the data stored in the internal RAM, distinguishes whether phase bits received with the data and also stored in the internal RAM are valid, and processes the data stored in the internal RAM when the phase bits are valid.

Abstract translation: 存储装置包括非易失性存储器和被配置为根据从外部设备接收的命令和地址将从外部设备接收的数据存储在内部RAM中的设备控制器。 设备控制器根据存储在内部RAM中的数据来控制非易失性存储器，区分在数据中存储的并且存储在内部RAM中的相位是否有效，并且当相位有效时处理存储在内部RAM中的数据 。

公开(公告)号：US20220019357A1

公开(公告)日：2022-01-20

申请号：US17225710

申请日：2021-04-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNGJIN CHO

IPC: G06F3/06 ,  G06F7/58

Abstract: A storage controller including: a host interface circuit receiving first, second, third and fourth requests corresponding to first, second, third and fourth logical addresses; a memory interface circuit communicating with first nonvolatile memories through a first channel and second nonvolatile memories through a second channel; a first flash translation layer configured to manage the first nonvolatile memories; and a second flash translation layer configured to manage the second nonvolatile memories, the first flash translation layer outputs commands corresponding to the first and fourth requests through the first channel, and the second flash translation layer outputs commands respectively corresponding to the second and third requests through the second channel, and a value of the first logical address is smaller than a value of the second logical address, and a value of the third logical address is smaller than a value of the fourth logical address.

公开(公告)号：US20200183619A1

公开(公告)日：2020-06-11

申请号：US16789526

申请日：2020-02-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JINWOO KIM ,  JAEGEUN PARK ,  YOUNGJIN CHO

IPC: G06F3/06 ,  G06F12/0868 ,  G06F11/10 ,  G06F13/28 ,  G06F12/0831

Abstract: A read method executed by a computing system includes a processor, at least one nonvolatile memory, and at least one cache memory performing a cache function of the at least one nonvolatile memory. The method includes receiving a read request regarding a critical word from the processor. A determination is made whether a cache miss is generated, through a tag determination operation corresponding to the read request. Page data corresponding to the read request is received from the at least one nonvolatile memory in a wraparound scheme when a result of the tag determination operation indicates that the cache miss is generated. The critical word is output to the processor when the critical word of the page data is received.

公开(公告)号：US20190266114A1

公开(公告)日：2019-08-29

申请号：US16411330

申请日：2019-05-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HAN-JU LEE ,  YOUNGKWANG YOO ,  YOUNGJIN CHO

IPC: G06F13/16 ,  G06F13/40

Abstract: A storage device includes random access memories, nonvolatile memory devices, a controller configured to control the nonvolatile memory devices, and a driver circuit configured to receive a command and an address from an external device, output a buffer command according to the command and the address, and transmit the command and the address to one of a first channel connected to the random access devices and a second channel connected to the controller according to the command and the address. The storage device further includes a plurality of data buffers configured to communicate with the external device and electrically connect the external device to one of a third channel connected to the random access memory devices and a fourth channel connected to the controller in response to the buffer command. Each of the data buffers includes a FIFO (first-in first-out) circuit.

公开(公告)号：US20170075829A1

公开(公告)日：2017-03-16

申请号：US15260916

申请日：2016-09-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HAN-JU LEE ,  YOUNGKWANG YOO ,  YOUNGJIN CHO

IPC: G06F13/16 ,  G06F13/40

CPC classification number: G06F13/1673 ,  G06F13/4072

Abstract: A storage device includes random access memories, nonvolatile memory devices, a controller configured to control the nonvolatile memory devices, and a driver circuit configured to receive a command and an address from an external device, output a buffer command according to the command and the address, and transmit the command and the address to one of a first channel connected to the random access devices and a second channel connected to the controller according to the command and the address. The storage device further includes a plurality of data buffers configured to communicate with the external device and electrically connect the external device to one of a third channel connected to the random access memory devices and a fourth channel connected to the controller in response to the buffer command. Each of the data buffers includes a FIFO (first-in first-out) circuit.

Abstract translation: 存储装置包括随机存取存储器，非易失性存储器件，被配置为控制非易失性存储器件的控制器和被配置为从外部设备接收命令和地址的驱动器电路，根据命令和地址输出缓冲器命令 并且将命令和地址发送到连接到随机接入设备的第一信道中的一个，以及根据命令和地址连接到控制器的第二信道。 存储设备还包括多个数据缓冲器，其被配置为与外部设备进行通信，并且将外部设备电连接到连接到随机存取存储器设备的第三通道中的一个和响应于缓冲器命令连接到控制器的第四通道 。 每个数据缓冲器包括FIFO（先入先出）电路。

公开(公告)号：US20170062040A1

公开(公告)日：2017-03-02

申请号：US15249333

申请日：2016-08-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： YOUNGJIN CHO ,  JAEGEUN PARK ,  Youngkwang YOO

IPC: G11C11/4074 ,  G11C7/10 ,  G06F1/32 ,  G11C11/406

CPC classification number: G11C11/4074 ,  G06F1/3287 ,  G11C11/40615 ,  G11C11/40626 ,  G11C2211/4067

Abstract: A dynamic random access memory (DRAM) device includes a memory cell array including a plurality of memory cells, a refresh controller configured to perform a plurality of refresh operations on the plurality of memory cells in response to a plurality of refresh commands from an external device, and a refresh counter configured to count a number of the refresh commands for a fixed period of time and compare the counted number with a threshold. The refresh counter is configured to generate a power failure signal to cause the DRAM device to enter a power failure mode in response to the comparison of the counted number with the threshold. The refresh controller is configured to perform a refresh operation on the plurality of memory cells without control of the external device in the power failure mode.

Abstract translation: 动态随机存取存储器（DRAM）装置包括包括多个存储器单元的存储单元阵列，刷新控制器，被配置为响应于来自外部设备的多个刷新命令对所述多个存储器单元执行多个刷新操作 以及刷新计数器，被配置为在固定时间段内对多个刷新命令进行计数，并将计数的数量与阈值进行比较。 刷新计数器被配置为响应于计数的数量与阈值的比较而产生电源故障信号以使DRAM设备进入电源故障模式。 刷新控制器被配置为在电源故障模式下不对外部设备进行控制，对多个存储单元执行刷新操作。

公开(公告)号：US20170060416A1

公开(公告)日：2017-03-02

申请号：US15188183

申请日：2016-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： YOUNGJIN CHO ,  HEE HYUN NAM ,  HYO-DEOK SHIN ,  JUNGHWAN RYU

IPC: G06F3/06 ,  G06F12/06

CPC classification number: G06F3/0659 ,  G06F3/0613 ,  G06F3/068 ,  G11C16/10

Abstract: A method of operating a memory module can include receiving, at the memory module, an active command and an associated row address that indicates that the active command is directed to a volatile memory device included in the memory module or to a non-volatile memory device included in the memory module. The volatile memory device or the non-volatile memory device can be activated based on the associated row address in response to the active command. Status information can be provided at the memory module indicating readiness of the memory module for receipt of an operation command associated with the active command and the associated row address

Abstract translation: 操作存储器模块的方法可以包括在存储器模块处接收活动命令和相关联的行地址，其指示活动命令被引导到包括在存储器模块中的易失性存储器装置或非易失性存储器装置 包含在内存模块中。 响应于活动命令，可以基于相关联的行地址来激活易失性存储器件或非易失性存储器件。 可以在存储器模块处提供状态信息，指示存储器模块的准备状态用于接收与活动命令相关联的操作命令和相关联的行地址

公开(公告)号：US20160358657A1

公开(公告)日：2016-12-08

申请号：US15083834

申请日：2016-03-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JINWOO KIM ,  SEONG YEON KIM ,  JAEGEUN PARK ,  HYO-DEOK SHIN ,  YOUNGGEUN LEE ,  YOUNGJIN CHO

IPC: G11C16/10

CPC classification number: G11C16/10 ,  G11C7/1063

Abstract: A nonvolatile memory system includes first and second nonvolatile memory devices and a memory controller configured to control the first and second nonvolatile memory devices through one channel. During a program operation, the memory controller transmits first signals, for setting first page data up in the first nonvolatile memory device, to the first nonvolatile memory device through the channel. While the first nonvolatile memory device sets up the first page data in response to the first signals, the memory controller transmits second signals, for setting second page data up in the second nonvolatile memory device, to the second nonvolatile memory device.

Abstract translation: 非易失性存储器系统包括第一和第二非易失性存储器件以及被配置为通过一个通道来控制第一和第二非易失性存储器件的存储器控​​制器。 在程序操作期间，存储器控制器通过通道向第一非易失性存储器件发送用于将第一非易失性存储器件中的第一页数据向上设置的第一信号。 当第一非易失性存储装置响应于第一信号设置第一页数据时，存储器控制器将用于将第二页数据向上设置在第二非易失存储装置中的第二信号发送到第二非易失存储装置。