公开(公告)号：US20230052799A1

公开(公告)日：2023-02-16

申请号：US17972804

申请日：2022-10-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JEONGHO LEE ,  YOUNGSIK KIM ,  SEUNGYOU BAEK ,  EUNCHU OH ,  YOUNGKWANG YOO ,  YOUNGGEUN LEE

IPC: G06F11/10 ,  G06F3/06

Abstract: A memory controller for controlling a memory operation of a memory device includes: an error correction code (ECC) circuit configured to detect an error of first read data read from the memory device and correct the error; an error type detection logic configured to write first write data to the memory device, compare second read data with the first write data, detect an error bit of the second read data based on a result of the comparing, and output information about an error type identified by the error bit; and a data patterning logic configured to change a bit pattern of input data to reduce an error of the second read data based on the information about the error type.

公开(公告)号：US20220027232A1

公开(公告)日：2022-01-27

申请号：US17495632

申请日：2021-10-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JEONGHO LEE ,  YOUNGSIK KIM ,  SEUNGYOU BAEK ,  YOUNGKWANG YOO ,  YOUNGGEUN LEE ,  YENA LEE

IPC: G06F11/10 ,  G06F11/30 ,  G06F9/54 ,  G11C13/00 ,  G06F12/02 ,  G06F9/30

Abstract: An operating method of a memory device, which includes a first memory region and a second memory region, includes reading first data from the first memory region and storing the read first data in a data buffer block, performing a first XOR operation on the first data provided from the data buffer block and second data read from the second memory region to generate first result data, writing the first data stored in the data buffer block in the second memory region, performing a second XOR operation on the first data and the first result data to generate the second data, storing the generated second data in the data buffer block, and writing the second data stored in the data buffer block in the first memory region.

公开(公告)号：US20200341843A1

公开(公告)日：2020-10-29

申请号：US16840581

申请日：2020-04-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JEONGHO LEE ,  YOUNGSIK KIM ,  SEUNGYOU BAEK ,  EUNCHU OH ,  YOUNGKWANG YOO ,  YOUNGGEUN LEE

IPC: G06F11/10 ,  G06F3/06

Abstract: A memory controller for controlling a memory operation of a memory device includes: an error correction code (ECC) circuit configured to detect an error of first read data read from the memory device and correct the error; an error type detection logic configured to write first write data to the memory device, compare second read data with the first write data, detect an error bit of the second read data based on a result of the comparing, and output information about an error type identified by the error bit; and a data patterning logic configured to change a bit pattern of input data to reduce an error of the second read data based on the information about the error type.

公开(公告)号：US20220012128A1

公开(公告)日：2022-01-13

申请号：US17448995

申请日：2021-09-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JEONGHO LEE ,  YOUNGSIK KIM ,  SEUNGYOU BAEK ,  EUNCHU OH ,  YOUNGKWANG YOO ,  YOUNGGEUN LEE

IPC: G06F11/10 ,  G06F3/06

Abstract: A memory controller for controlling a memory operation of a memory device includes: an error correction code (ECC) circuit configured to detect an error of first read data read from the memory device and correct the error; an error type detection logic configured to write first write data to the memory device, compare second read data with the first write data, detect an error bit of the second read data based on a result of the comparing, and output information about an error type identified by the error bit; and a data patterning logic configured to change a bit pattern of input data to reduce an error of the second read data based on the information about the error type.

公开(公告)号：US20200319962A1

公开(公告)日：2020-10-08

申请号：US16695395

申请日：2019-11-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JEONGHO LEE ,  YOUNGSIK KIM ,  SEUNGYOU BAEK ,  YOUNGKWANG YOO ,  YOUNGGEUN LEE ,  YENA LEE

IPC: G06F11/10 ,  G06F11/30 ,  G06F9/54 ,  G06F9/30 ,  G06F12/02 ,  G11C13/00

Abstract: An operating method of a memory device, which includes a first memory region and a second memory region, includes reading first data from the first memory region and storing the read first data in a data buffer block, performing a first XOR operation on the first data provided from the data buffer block and second data read from the second memory region to generate first result data, writing the first data stored in the data buffer block in the second memory region, performing a second XOR operation on the first data and the first result data to generate the second data, storing the generated second data in the data buffer block, and writing the second data stored in the data buffer block in the first memory region.

公开(公告)号：US20190266114A1

公开(公告)日：2019-08-29

申请号：US16411330

申请日：2019-05-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HAN-JU LEE ,  YOUNGKWANG YOO ,  YOUNGJIN CHO

IPC: G06F13/16 ,  G06F13/40

Abstract: A storage device includes random access memories, nonvolatile memory devices, a controller configured to control the nonvolatile memory devices, and a driver circuit configured to receive a command and an address from an external device, output a buffer command according to the command and the address, and transmit the command and the address to one of a first channel connected to the random access devices and a second channel connected to the controller according to the command and the address. The storage device further includes a plurality of data buffers configured to communicate with the external device and electrically connect the external device to one of a third channel connected to the random access memory devices and a fourth channel connected to the controller in response to the buffer command. Each of the data buffers includes a FIFO (first-in first-out) circuit.

公开(公告)号：US20170075829A1

公开(公告)日：2017-03-16

申请号：US15260916

申请日：2016-09-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HAN-JU LEE ,  YOUNGKWANG YOO ,  YOUNGJIN CHO

IPC: G06F13/16 ,  G06F13/40

CPC classification number: G06F13/1673 ,  G06F13/4072

Abstract: A storage device includes random access memories, nonvolatile memory devices, a controller configured to control the nonvolatile memory devices, and a driver circuit configured to receive a command and an address from an external device, output a buffer command according to the command and the address, and transmit the command and the address to one of a first channel connected to the random access devices and a second channel connected to the controller according to the command and the address. The storage device further includes a plurality of data buffers configured to communicate with the external device and electrically connect the external device to one of a third channel connected to the random access memory devices and a fourth channel connected to the controller in response to the buffer command. Each of the data buffers includes a FIFO (first-in first-out) circuit.

Abstract translation: 存储装置包括随机存取存储器，非易失性存储器件，被配置为控制非易失性存储器件的控制器和被配置为从外部设备接收命令和地址的驱动器电路，根据命令和地址输出缓冲器命令 并且将命令和地址发送到连接到随机接入设备的第一信道中的一个，以及根据命令和地址连接到控制器的第二信道。 存储设备还包括多个数据缓冲器，其被配置为与外部设备进行通信，并且将外部设备电连接到连接到随机存取存储器设备的第三通道中的一个和响应于缓冲器命令连接到控制器的第四通道 。 每个数据缓冲器包括FIFO（先入先出）电路。

公开(公告)号：US20210406125A1

公开(公告)日：2021-12-30

申请号：US17469377

申请日：2021-09-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JEONGHO LEE ,  YOUNGSIK KIM ,  SEUNGYOU BAEK ,  EUNCHU OH ,  YOUNGKWANG YOO ,  YOUNGGEUN LEE

IPC: G06F11/10 ,  G06F3/06

Abstract: A memory controller for controlling a memory operation of a memory device includes: an error correction code (ECC) circuit configured to detect an error of first read data read from the memory device and correct the error; an error type detection logic configured to write first write data to the memory device, compare second read data with the first write data, detect an error bit of the second read data based on a result of the comparing, and output information about an error type identified by the error bit; and a data patterning logic configured to change a bit pattern of input data to reduce an error of the second read data based on the information about the error type.

公开(公告)号：US20190354474A1

公开(公告)日：2019-11-21

申请号：US16195533

申请日：2018-11-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HAN-JU LEE ,  YOUNGJIN CHO ,  SUNGYONG SEO ,  YOUNGKWANG YOO

IPC: G06F12/02 ,  G06F3/06 ,  G06F13/16 ,  G06F13/42 ,  G06F12/06

Abstract: The nonvolatile memory module includes at least one nonvolatile memory device and a device controller configured to receive a storage command from an external device and to perform an operation corresponding to the received storage command The device controller includes a random access memory (RAM). After completing the corresponding operation, the device controller stores status information in the RAM and then transmits an alert signal to the external device.

公开(公告)号：US20190205037A1

公开(公告)日：2019-07-04

申请号：US16298318

申请日：2019-03-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HAN-JU LEE ,  YOUNGKWANG YOO ,  YOUNGJIN CHO

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0688 ,  G06F13/385

Abstract: A storage device includes a data buffer, a device controller, and nonvolatile memories. The data buffer is configured to transact data from an external device. The device controller is configured to receive a command and an address from an external device, to control the data buffers, and to transact data with the data buffers. The nonvolatile memories are configured to perform write, read, and erase operations under control of the device controller. When a first link training between an external device and the data buffers is performed by the external device, the device controller performs a second link training between the device controller and a data buffer internally without control of the external device.