公开(公告)号：US20240003007A1

公开(公告)日：2024-01-04

申请号：US18138192

申请日：2023-04-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： PYUNG MOON ,  KIHYUN KIM ,  HYOUNGSUB KIM ,  HOIJOON KIM ,  GEUNYOUNG YEOM ,  KONGSOO LEE ,  HEESOO LEE

IPC: C23C16/455 ,  H01J37/32 ,  H01L29/16 ,  H01L29/51

CPC classification number: C23C16/45536 ,  H01L29/517 ,  H01L29/1606 ,  H01J37/32357

Abstract: A method of manufacturing an integrated circuit device includes alternately stacking sacrificial semiconductor layers and channel layers on a substrate to form a stack structure, forming source regions and drain regions on both sides of the stack structure, forming a gate space between the channel layers by removing the sacrificial semiconductor layers, forming the channel layers to be spaced apart from each other in a perpendicular direction to the substrate, performing a plasma treatment of boron trichloride (BCL3) on the channel layers, forming gate dielectric layers on the channel layers on which the plasma treatment of boron trichloride (BCL3) is performed, and forming gate layers covering the gate dielectric layers in the gate space.