公开(公告)号：US20180190709A1

公开(公告)日：2018-07-05

申请号：US15800376

申请日：2017-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Haewon LEE ,  Sangjoo LEE ,  Moosup LIM ,  Younghwan PARK ,  Dongjoo YANG ,  Kang-Sun LEE ,  Jiwon LEE

IPC: H01L27/146 ,  H01L31/02 ,  H04N5/374 ,  H04N5/378

CPC classification number: H01L27/14654 ,  H01L27/14607 ,  H01L27/14612 ,  H01L27/1463 ,  H01L31/02019 ,  H04N5/3591 ,  H04N5/374 ,  H04N5/37457 ,  H04N5/378

Abstract: An image sensor includes a separation impurity layer in a semiconductor layer and defining a photoelectric conversion region and a readout circuit region, a photoelectric conversion layer in the semiconductor layer of the photoelectric conversion region and surrounded by the separation impurity layer, a floating diffusion region spaced apart from the photoelectric conversion layer and in the semiconductor layer of the photoelectric conversion region, a transfer gate electrode between the photoelectric conversion layer and the floating diffusion region, and impurity regions in the semiconductor layer of the readout circuit region. When the photoelectric conversion layer is integrated with photo-charges, the separation impurity layer has a first potential level around the photoelectric conversion layer and a second potential level on a portion between the photoelectric conversion layer and the impurity regions of the readout circuit region. The second potential level is greater than the first potential level.

公开(公告)号：US20240111433A1

公开(公告)日：2024-04-04

申请号：US18199566

申请日：2023-05-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Kyu KANG ,  Jieun SHIN ,  Ho-Cheol BANG ,  Haewon LEE

IPC: G06F3/06 ,  G06F1/08

CPC classification number: G06F3/0619 ,  G06F1/08 ,  G06F3/0653 ,  G06F3/0673

Abstract: In some embodiments, a memory system includes a memory device and a host configured to transmit, to the memory device, a command and address (C/A) signal and a clock signal, and to transmit or receive data signals to or from the memory device. Each command that is configured to access the memory device is associated with an access timing parameter. The memory device includes an access parameter timer configured to measure an actual timing value of the access timing parameter, a spec register configured to provide a spec timing value defining an effective timing of the access timing parameter, a comparison circuit configured to compare the actual timing value and the spec timing value, and a mode register configured to store an access timing violation flag that is read by the host when the actual timing value deviates from the spec timing value by exceeding a predetermined range.