公开(公告)号：US20230214329A1

公开(公告)日：2023-07-06

申请号：US17820631

申请日：2022-08-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Moon WOO ,  Seon Bong KIM ,  Han-Ju LEE

IPC: G06F12/1045 ,  G06F12/1081 ,  G06F12/0862

CPC classification number: G06F12/1045 ,  G06F12/1081 ,  G06F12/0862

Abstract: A storage device includes a storage controller and a host interface which sends an address translation service request to a host. The host interface includes an address translation cache which stores first address information included in the address translation service request, and an address translation service latency storage which stores latency-related information including a first time until the address translation cache receives an address translation service response corresponding to the address translation service request from the host. After the host interface sends the address translation service request to the host based on the latency-related information including the first time, and after the first time elapses, the storage controller polls the host interface.

公开(公告)号：US20170235524A1

公开(公告)日：2017-08-17

申请号：US15421514

申请日：2017-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngkwang YOO ,  Youngjin CHO ,  Han-Ju LEE ,  JinHyeok CHOI

IPC: G06F3/06 ,  G06F12/0868

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0685 ,  G06F12/0868 ,  G06F2212/1016 ,  G06F2212/202 ,  G11C8/12 ,  G11C2207/2245

Abstract: A nonvolatile memory module may include a nonvolatile memory device, a nonvolatile memory controller configured to control the nonvolatile memory device, a volatile memory device configured as a cache memory of the nonvolatile memory device, and a module controller configured to receive a command and an address from an external device, external to the nonvolatile memory module, and to send a volatile memory command and a volatile memory address to the volatile memory device through a first bus and a nonvolatile memory command and a nonvolatile memory address to the controller through a second bus in response to the received command and address. The volatile memory device is configured to load two or more cache data on each of two or more memory data line groups and two or more tags on each of two or more tag data line groups in response to the volatile memory address.