公开(公告)号：US20170153826A1

公开(公告)日：2017-06-01

申请号：US15366137

申请日：2016-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngjin CHO ,  Sungyong SEO ,  Sun-Young LIM ,  Uksong KANG ,  Chankyung KIM ,  Duckhyun CHANG ,  JinHyeok CHOI

IPC: G06F3/06 ,  G06F12/0893 ,  G11C16/10 ,  G06F12/0868 ,  G11C14/00 ,  G11C16/26

CPC classification number: G06F3/0611 ,  G06F3/0656 ,  G06F3/0679 ,  G06F12/0868 ,  G06F12/0893 ,  G06F13/16 ,  G06F2212/1021 ,  G06F2212/1024 ,  G06F2212/205 ,  G06F2212/214 ,  G06F2212/3042 ,  G06F2212/305 ,  G06F2212/313 ,  G06F2212/7203 ,  G11C11/005 ,  G11C16/10 ,  G11C16/26 ,  G11C2207/2245

Abstract: A nonvolatile memory device includes a nonvolatile memory, a volatile memory being a cache memory of the nonvolatile memory, and a first controller configured to control the nonvolatile memory. The nonvolatile memory device further includes a second controller configured to receive a device write command and an address, and transmit, to the volatile memory through a first bus, a first read command and the address and a first write command and the address sequentially, and transmit a second write command and the address to the first controller through a second bus, in response to the reception of the device write command and the address.

公开(公告)号：US20210357130A1

公开(公告)日：2021-11-18

申请号：US17389834

申请日：2021-07-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngjin CHO ,  Sungyong SEO ,  Sun-Young LIM ,  Uksong KANG ,  Chankyung KIM ,  Duckhyun CHANG ,  JinHyeok CHOI

IPC: G06F3/06 ,  G11C16/26 ,  G11C16/10 ,  G06F12/0868 ,  G06F12/0893 ,  G11C11/00 ,  G06F13/16

Abstract: A nonvolatile memory device includes a nonvolatile memory, a volatile memory being a cache memory of the nonvolatile memory, and a first controller configured to control the nonvolatile memory. The nonvolatile memory device further includes a second controller configured to receive a device write command and an address, and transmit, to the volatile memory through a first bus, a first read command and the address and a first write command and the address sequentially, and transmit a second write command and the address to the first controller through a second bus, in response to the reception of the device write command and the address.

公开(公告)号：US20180088854A1

公开(公告)日：2018-03-29

申请号：US15697900

申请日：2017-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwanwoo NOH ,  Hyuntae PARK ,  Sungho SEO ,  Hwaseok OH ,  Youngmin LEE ,  JinHyeok CHOI

IPC: G06F3/06 ,  G06F13/42

CPC classification number: G06F3/0634 ,  G06F3/0611 ,  G06F3/0632 ,  G06F11/0787 ,  G06F13/4239 ,  G06F13/4247 ,  G11C5/04

Abstract: An electronic device includes an application processor; and a first storage device that is, connected to the application processor and directly communicates with the application processor, and connected to a second storage device such that the second storage device communicates with the application processor through the first storage device, wherein the first storage device includes a reset converter configured to generate a software reset signal in response to a hardware reset signal received from the application processor, and wherein the software reset signal resets the second storage device.

公开(公告)号：US20170235524A1

公开(公告)日：2017-08-17

申请号：US15421514

申请日：2017-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngkwang YOO ,  Youngjin CHO ,  Han-Ju LEE ,  JinHyeok CHOI

IPC: G06F3/06 ,  G06F12/0868

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0685 ,  G06F12/0868 ,  G06F2212/1016 ,  G06F2212/202 ,  G11C8/12 ,  G11C2207/2245

Abstract: A nonvolatile memory module may include a nonvolatile memory device, a nonvolatile memory controller configured to control the nonvolatile memory device, a volatile memory device configured as a cache memory of the nonvolatile memory device, and a module controller configured to receive a command and an address from an external device, external to the nonvolatile memory module, and to send a volatile memory command and a volatile memory address to the volatile memory device through a first bus and a nonvolatile memory command and a nonvolatile memory address to the controller through a second bus in response to the received command and address. The volatile memory device is configured to load two or more cache data on each of two or more memory data line groups and two or more tags on each of two or more tag data line groups in response to the volatile memory address.

公开(公告)号：US20200051601A1

公开(公告)日：2020-02-13

申请号：US16655782

申请日：2019-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongwoo JEONG ,  Hwaseok OH ,  JinHyeok CHOI

IPC: G11C7/22 ,  G11C7/10 ,  G11C16/08 ,  G11C16/32 ,  G11C29/02

Abstract: Disclosed is an electronic device which includes an application processor configured to generate a reference clock, a first storage device configured to receive the reference clock from the application processor through a clock input port, to output the reference clock to a clock output port, and to communicate with the application processor by using the reference clock, and a second storage device configured to receive the reference clock from the clock output port and use the reference clock for communication with the first storage device.

公开(公告)号：US20180090191A1

公开(公告)日：2018-03-29

申请号：US15685654

申请日：2017-08-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongwoo JEONG ,  Hwaseok OH ,  JinHyeok CHOI

IPC: G11C7/22 ,  G11C16/08 ,  G11C16/32 ,  G11C7/10

CPC classification number: G11C7/22 ,  G11C7/10 ,  G11C7/1045 ,  G11C7/222 ,  G11C8/12 ,  G11C16/08 ,  G11C16/32 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012

Abstract: Disclosed is an electronic device which includes an application processor configured to generate a reference clock, a first storage device configured to receive the reference clock from the application processor through a clock input port, to output the reference clock to a clock output port, and to communicate with the application processor by using the reference clock, and a second storage device configured to receive the reference clock from the clock output port and use the reference clock for communication with the first storage device.

公开(公告)号：US20180081556A1

公开(公告)日：2018-03-22

申请号：US15681574

申请日：2017-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngmin LEE ,  Ji-Seung YOUN ,  Sungho SEO ,  Hyuntae PARK ,  Hwaseok OH ,  JinHyeok CHOI

IPC: G06F3/06

CPC classification number: G06F3/0607 ,  G06F3/061 ,  G06F3/064 ,  G06F3/0661 ,  G06F3/0683 ,  G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7202 ,  G06F2212/7203 ,  G06F2212/7207

Abstract: Disclosed is a storage device which includes a nonvolatile memory device and a controller. The controller communicates with a host through a first port, communicates with an external storage device through a second port, and controls the nonvolatile memory device based on first mapping information. The controller is configured to receive second mapping information from the external storage device, receive first write data from the host and to selectively transmit first write data to the external storage device based on the second mapping information.