公开(公告)号：US20130337643A1

公开(公告)日：2013-12-19

申请号：US13804398

申请日：2013-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho-Jun SEONG ,  Jae-Hwang SIM

IPC: H01L29/66

CPC classification number: H01L29/66477 ,  H01L21/28273 ,  H01L27/0629 ,  H01L27/11521 ,  H01L28/20 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method of fabricating a semiconductor device includes etching a substrate to form a field trench defining an active region and a lower gate pattern on the active region, the lower gate pattern including a tunneling insulating pattern and a lower gate electrode pattern, filling a field insulating material in the field trench to form a field region, forming an upper gate pattern on the lower gate pattern, sequentially forming a stopping layer and a buffer layer on the field region and the upper gate pattern, forming a first resistive pattern on the buffer layer of the field region, and forming a second resistive pattern on the buffer layer on the upper gate pattern, forming an interlayer insulating layer covering the first and second resistive patterns, and performing a planarization process to remove a top surface of the interlayer insulating layer and to remove the second resistive pattern.

Abstract translation: 一种制造半导体器件的方法包括蚀刻衬底以形成在有源区上限定有源区和下栅极图案的场沟槽，下栅极图案包括隧道绝缘图案和下栅极电极图案，填充场绝缘 在沟槽中形成场区域，在下栅极图案上形成上栅极图案，在场区域和上栅极图案上依次形成停止层和缓冲层，在缓冲层上形成第一电阻图案 并且在上栅极图案上的缓冲层上形成第二电阻图案，形成覆盖第一和第二电阻图案的层间绝缘层，并执行平面化处理以去除层间绝缘层的顶表面，以及 以去除第二电阻图案。

公开(公告)号：US20160056170A1

公开(公告)日：2016-02-25

申请号：US14734287

申请日：2015-06-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-Jun SEONG ,  Jee-hoon HAN

IPC: H01L27/115 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/28 ,  H01L21/311

CPC classification number: H01L21/768 ,  H01L21/0337 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/32139 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11531 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573

Abstract: A method of fabricating a flash memory device includes sequentially forming an etching object layer and a lower sacrificial layer on a substrate, and forming an upper sacrificial pattern structure on the lower sacrificial layer. The upper sacrificial pattern structure includes an upper sacrificial pad portion and an upper sacrificial line portion on the lower sacrificial layer. An upper spacer is formed by covering a side wall of the upper sacrificial pattern structure. A lower sacrificial pattern structure including a lower sacrificial pad portion and a lower sacrificial line portion is formed by etching the lower sacrificial layer, by using the upper sacrificial pad portion and the upper spacer as an etch mask. A lower spacer layer is formed by covering the lower sacrificial pattern structure. Finally, a lower mask pattern including at least one line mask, at least one bridge mask, and at least one pad mask, is formed by etching the lower spacer layer and the lower sacrificial pattern structure.

Abstract translation: 一种制造闪速存储器件的方法包括在衬底上顺序地形成蚀刻对象层和下牺牲层，并在下牺牲层上形成上牺牲图案结构。 上牺牲图案结构包括在下牺牲层上的上牺牲垫部分和上牺牲线部分。 通过覆盖上牺牲图案结构的侧壁形成上隔离物。 通过使用上部牺牲焊盘部分和上部间隔物作为蚀刻掩模，通过蚀刻下部牺牲层来形成包括下部牺牲焊盘部分和下部牺牲线部分的下部牺牲图案结构。 通过覆盖下牺牲图案结构形成下间隔层。 最后，通过蚀刻下间隔层和下牺牲图案结构形成包括至少一个线掩模，至少一个桥接掩模和至少一个焊盘掩模的下掩模图案。