公开(公告)号：US20240429187A1

公开(公告)日：2024-12-26

申请号：US18826451

申请日：2024-09-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Homoon Shin ,  Jooyong Park ,  Hongsoo Jeon ,  Pansuk Kwak

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

Abstract: An integrated circuit device includes; a peripheral circuit structure including a peripheral circuit, a first insulating layer covering the peripheral circuit, extension lines in the first insulating layer, and a first bonding pad in the first insulating layer, and a cell array structure including a conductive plate, a memory cell array below the conductive plate, a second insulating layer covering the memory cell array, a second bonding pad in the second insulating layer, a conductive via on the conductive plate, and a line connected to the conductive via. The first bonding pad contacts the second bonding pad, and the integrated circuit device further includes contact plugs electrically connecting the line to the extension lines.

公开(公告)号：US12107061B2

公开(公告)日：2024-10-01

申请号：US17513132

申请日：2021-10-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Homoon Shin ,  Jooyong Park ,  Hongsoo Jeon ,  Pansuk Kwak

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: An integrated circuit device includes; a peripheral circuit structure including a peripheral circuit, a first insulating layer covering the peripheral circuit, extension lines in the first insulating layer, and a first bonding pad in the first insulating layer, and a cell array structure including a conductive plate, a memory cell array below the conductive plate, a second insulating layer covering the memory cell array, a second bonding pad in the second insulating layer, a conductive via on the conductive plate, and a line connected to the conductive via. The first bonding pad contacts the second bonding pad, and the integrated circuit device further includes contact plugs electrically connecting the line to the extension lines.

公开(公告)号：US11894055B2

公开(公告)日：2024-02-06

申请号：US17578840

申请日：2022-01-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ansoo Park ,  Ahreum Kim ,  Homoon Shin

IPC: G11C7/00 ,  G11C16/08 ,  G11C16/30

CPC classification number: G11C16/08 ,  G11C16/30

Abstract: A semiconductor device includes: a peripheral circuit region including circuit elements on a substrate, the circuit elements of a page buffer and a row decoder; and a cell region including gate electrode layers, stacked in a first direction, perpendicular to an upper surface of the substrate, and connected to the row decoder, and channel structures extending in the first direction to penetrate through the gate electrode layers and to be connected to the page buffer. The row decoder includes high-voltage elements, operating at a first power supply voltage, and low-voltage elements operating at a second power supply voltage, lower than the first power supply voltage. Among the high-voltage elements, at least one first high-voltage device is in a first well region doped with impurities having a first conductivity-type. At least one of the low-voltage elements is in a second well region surrounding the first well region and doped with impurities having a second conductivity-type, different from the first conductivity-type.

公开(公告)号：US11437088B2

公开(公告)日：2022-09-06

申请号：US17239655

申请日：2021-04-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngjae Kim ,  Jincheol Kim ,  Ahreum Kim ,  Homoon Shin ,  Dooho Cho ,  Yongsung Cho

IPC: G11C11/408 ,  G11C11/4074 ,  G11C11/4093 ,  G11C5/06

Abstract: A nonvolatile memory includes; a memory cell array including memory cells commonly connected to a first signal line, a first row decoder including a first pass transistor configured to provide a driving voltage to one end of the first signal line, and a second row decoder including a second pass transistor configured to provide the driving voltage to an opposing end of the first signal line. An ON-resistance of the first pass transistor is different from an ON-resistance of the second pass transistor. A first wiring line having a first resistance connects the first pass transistor and the one end of the first signal line and a second wiring line having a second resistance different from the first resistance connects the second pass transistor and the opposing end of the first signal line.