公开(公告)号：US12074142B2

公开(公告)日：2024-08-27

申请号：US17669773

申请日：2022-02-11

申请人： Samsung Electronics Co., Ltd.

发明人： Jongpa Hong ,  Hwail Jin ,  Sang-Sick Park

IPC分类号： H01L21/00 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L25/0657 ,  H01L23/3157 ,  H01L23/481 ,  H01L24/16 ,  H01L24/17 ,  H01L24/73 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/16146 ,  H01L2224/17177 ,  H01L2224/73204 ,  H01L2224/81203

摘要： Disclosed are semiconductor packages and their fabricating methods. The semiconductor package comprises connection terminals between a first die and a second die. The first die has signal and peripheral regions and includes first vias on the peripheral region. The second die is on the first die and has second vias on positions that correspond to the first vias. The connection terminals connect the second vias to the first vias. The peripheral region includes first regions adjacent to corners of the first die and second regions adjacent to lateral surfaces of the first die. The connection terminals include first connection terminals on the first regions and second connection terminals on the second regions. A sum of areas of the first connection terminals per unit area on the first regions is greater than that of areas of the second connection terminals per unit area on the second regions.

公开(公告)号：US11842982B2

公开(公告)日：2023-12-12

申请号：US17329230

申请日：2021-05-25

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Seon Ho Lee ,  Hwail Jin ,  Jongpa Hong

IPC分类号： H01L25/065 ,  H01L25/00

CPC分类号： H01L25/0652 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06586

摘要： A semiconductor package includes a lower semiconductor chip having a lower semiconductor substrate and upper pads on a top surface of the lower semiconductor substrate, an upper semiconductor chip stacked on the lower semiconductor chip, the upper semiconductor chip including an upper semiconductor substrate and solder bumps on a bottom surface of the upper semiconductor substrate, and a curing layer between the lower semiconductor chip and the upper semiconductor chip, the curing layer including a first curing layer adjacent to the upper semiconductor chip, the first curing layer including a first photo-curing agent, and a second curing layer between the first curing layer and the top surface of the lower semiconductor substrate, the second curing layer including a first thermo-curing agent.

公开(公告)号：US12040213B2

公开(公告)日：2024-07-16

申请号：US17191163

申请日：2021-03-03

申请人： Samsung Electronics Co., Ltd.

发明人： Hwail Jin ,  Seon Ho Lee ,  Yeongseok Kim

IPC分类号： H01L21/78 ,  C09J7/24 ,  C09J7/38 ,  C09J7/40 ,  H01L21/683

CPC分类号： H01L21/6836 ,  C09J7/241 ,  C09J7/385 ,  C09J7/401 ,  C09J7/403 ,  H01L21/78 ,  C09J2423/006 ,  C09J2433/005 ,  C09J2483/005 ,  Y10T428/14 ,  Y10T428/1457 ,  Y10T428/1476

摘要： A processing tape may include a base layer, an adhesive layer disposed on the base layer, a protection release film on the adhesive layer, and a first release layer interposed between the adhesive layer and the protection release film. The first release layer may include a silicone-based material and may be non-photo-curable.

公开(公告)号：US10910339B2

公开(公告)日：2021-02-02

申请号：US16533450

申请日：2019-08-06

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Hwail Jin ,  Yongwon Choi ,  Myung-Sung Kang ,  Yeongseok Kim ,  Wonkeun Kim

IPC分类号： H01L23/00 ,  H01L21/78

摘要： A flip chip bonding method includes obtaining a die including a first substrate and an adhesive layer on the first substrate; bonding the die to a second substrate different from the first substrate; and curing the adhesive layer. The curing the adhesive layer includes heating the second substrate to melt the adhesive layer, and providing the adhesive layer and the second substrate with air having pressure greater than atmospheric pressure.