公开(公告)号：US20240430140A1

公开(公告)日：2024-12-26

申请号：US18487389

申请日：2023-10-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyochang Kim

IPC: H04L25/03 ,  H04B1/12

Abstract: A receiver includes a decision feedback equalizer therein. The equalizer, which includes a cascaded arrangement of a first stage having a first plurality of summers therein and a second stage having a second plurality of summers therein, is configured to: (i) generate a compensated data signal by summing a current value of a data signal and a plurality of feedback signals, in response to a plurality of selection signals, (ii) generate a sampled signal including a decision value by sampling bits of the compensated data signal, in response to a plurality of divided strobe signals, and (iii) generate the feedback signals in response to a plurality of weights, the sampled signal, and at least one delayed version of the sampled signal.

公开(公告)号：US11955986B2

公开(公告)日：2024-04-09

申请号：US18096696

申请日：2023-01-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyochang Kim

IPC: H03M1/46 ,  H03K5/24

CPC classification number: H03M1/46 ,  H03K5/24

Abstract: A comparator circuit, including an input circuit, first and second inverting amplification circuits, first and second coupling circuits, and a feedback circuit, wherein the input circuit generates an amplified input signal based on positive and negative input voltages, the first inverting amplification circuit generates an intermediate amplified signal based on the amplified input signal during a sampling period, the second inverting amplification circuit generates a comparison result signal based on the intermediate amplified signal during the sampling period, the first coupling circuit is connected between the input circuit and the first inverting amplification circuit, the second coupling circuit is connected between the first inverting amplification circuit and the second inverting amplification circuit, and the feedback circuit amplifies the input node of the first inverting amplification circuit with a rail-to-rail voltage corresponding to a power supply voltage or a ground voltage based on the comparison result signal during the sampling period.

公开(公告)号：US20240333271A1

公开(公告)日：2024-10-03

申请号：US18493417

申请日：2023-10-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyochang Kim

IPC: H03K5/02 ,  H03F1/26 ,  H03F3/45 ,  H03K3/0233 ,  H03K5/08

CPC classification number: H03K5/02 ,  H03F1/26 ,  H03F3/45968 ,  H03K3/0233 ,  H03K5/082

Abstract: Disclosed is a differential chopper comparator, which includes an input terminal circuit that receives a first input signal and a second input signal and selectively switches the first and second input signals to intermediate circuit, at least one chopper circuit that generates a first amplified signal and a second amplified signal by amplifying a difference between the first and second input signals at the intermediate circuit points, a comparison circuit that compares the first amplified signal with the second amplified signal, digitizes the comparison result, and outputs a digital signal at a logic level, and a compensation circuit that offsets the first amplified signal and the second amplified signal and thereby removes kickback noise induced in the input terminal circuit. The differential chopper comparator of the present disclosure may shorten the settling time and may operate at high speed.

公开(公告)号：US20230368855A1

公开(公告)日：2023-11-16

申请号：US18061764

申请日：2022-12-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyochang Kim ,  Changsik Yoo

IPC: G11C29/02 ,  G11C7/10 ,  G11C7/06 ,  G11C7/22

CPC classification number: G11C29/023 ,  G11C7/1012 ,  G11C7/062 ,  G11C7/22

Abstract: A memory device includes a DC conversion circuit that receives a first edge-triggered phase signal having first pulses each extending from a rising edge of a first phase signal of a multiphase clock to a later rising edge of a second phase signal of the multiphase clock and a second edge-triggered phase signal having second pulses each extending from a rising edge of the second phase signal to a later rising edge of the first phase signal, and outputting a first voltage corresponding to the first edge-triggered phase signal and a second voltage corresponding to the second edge-triggered phase signal, a comparator that compares the first voltage with the second voltage, control logic that generates a control code corresponding to an output value from the comparator, and a delay cell that delays the second phase signal according to the control code.