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    SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME
    2.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME 有权

    公开(公告)号：US20220343957A1

    公开(公告)日：2022-10-27

    申请号：US17526398

    申请日：2021-11-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hojun Yoon ,  Youngchul Cho ,  Youngdon Choi ,  Changsik Yoo ,  Junghwan Choi

    IPC: G11C7/22 ,  G11C7/10

    Abstract: A semiconductor memory device includes a quadrature error correction circuit, a clock generation circuit and a data input/output (I/O) buffer. The quadrature error correction circuit performs a locking operation to generate a first corrected clock signal and a second corrected clock signal by adjusting a skew and a duty error of a first through fourth clock signals generated based on a data clock signal and performs a relocking operation to lock the second corrected clock signal to the first corrected clock signal in response to a relock signal. The clock generation circuit generates an output clock signal and a strobe signal based on the first corrected clock signal and the second corrected clock signal. The data I/O buffer generates a data signal by sampling data from a memory cell array based on the output clock signal and transmits the data signal and the strobe signal to a memory controller.

    Memory device and memory system including the same
    3.
    发明授权
    Memory device and memory system including the same 有权

    公开(公告)号：US11218343B2

    公开(公告)日：2022-01-04

    申请号：US17156813

    申请日：2021-01-25

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jaewoo Park ,  Youngdon Choi ,  Junghwan Choi ,  Changsik Yoo

    IPC: H04L25/02 ,  H04L25/14 ,  H04L25/49

    Abstract: Provided are a memory device and a memory system including the same. The memory device may include a data bus inversion (DBI) mode selector configured to select a first multi-bit DBI signal from among a plurality of multi-bit DBI signals respectively corresponding to a plurality of DBI modes according to multi-bit data; a multi-mode DBI encoder configured to generate encoded multi-bit data by DBI encoding the multi-bit data according to the first multi-bit DBI signal; and a transceiver configured to transmit a data symbol corresponding to the encoded multi-bit data through a data channel and transmit a DBI symbol corresponding to the first multi-bit DBI signal through a DBI channel.

    INTEGRATED CIRCUIT DEVICE
    4.
    发明公开
    INTEGRATED CIRCUIT DEVICE 审中-公开

    公开(公告)号：US20240304661A1

    公开(公告)日：2024-09-12

    申请号：US18598552

    申请日：2024-03-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Gina Lee ,  Seil Oh ,  Inseok Baek ,  Changsik Yoo

    IPC: H10B12/00

    CPC classification number: H01L28/90 ,  H10B12/30 ,  H10B12/50

    Abstract: An integrated circuit device includes a substrate including a cell array region and a peripheral circuit region, a first ion implantation region located in an upper portion of the substrate in the peripheral circuit region, the first ion implantation region having a plurality of line trenches that extend in a first horizontal direction and cross the first ion implantation region, a plurality of lower capacitor dielectric films with each lower capacitor dielectric film configured to respectively cover inner walls of a respective line trench, a plurality of buried conductive lines that each partially fill a respective line trench and that are each respectively disposed on a respective lower capacitor dielectric film, a plurality of first lower capacitor contacts that are each in contact with a respective buried conductive line, and a plurality of second lower capacitor contacts that are in contact with the first ion implantation region.

    Semiconductor memory device and memory system including the same
    6.
    发明授权
    Semiconductor memory device and memory system including the same 有权

    公开(公告)号：US11699472B2

    公开(公告)日：2023-07-11

    申请号：US17526398

    申请日：2021-11-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hojun Yoon ,  Youngchul Cho ,  Youngdon Choi ,  Changsik Yoo ,  Junghwan Choi

    IPC: G11C7/22 ,  G11C7/10

    CPC classification number: G11C7/222 ,  G11C7/1057 ,  G11C7/1084

    Abstract: A semiconductor memory device includes a quadrature error correction circuit, a clock generation circuit and a data input/output (I/O) buffer. The quadrature error correction circuit performs a locking operation to generate a first corrected clock signal and a second corrected clock signal by adjusting a skew and a duty error of a first through fourth clock signals generated based on a data clock signal and performs a relocking operation to lock the second corrected clock signal to the first corrected clock signal in response to a relock signal. The clock generation circuit generates an output clock signal and a strobe signal based on the first corrected clock signal and the second corrected clock signal. The data I/O buffer generates a data signal by sampling data from a memory cell array based on the output clock signal and transmits the data signal and the strobe signal to a memory controller.

    Semiconductor device with adjustment of phase of data signal and clock signals, and memory system including the same
    9.
    发明授权
    Semiconductor device with adjustment of phase of data signal and clock signals, and memory system including the same 有权

    公开(公告)号：US12205668B2

    公开(公告)日：2025-01-21

    申请号：US17722805

    申请日：2022-04-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jaemin Choi ,  Yonghun Kim ,  Jaewoo Jeong ,  Kyungryun Kim ,  Yoochang Sung ,  Changsik Yoo

    IPC: G11C7/10

    Abstract: A semiconductor device includes: a plurality of pads connected to a memory device receiving a data signal using first to fourth clock signals having different phases; a data transmission/reception circuit inputting and outputting the data signal to a plurality of data pads of the plurality of pads and including a data delay cell adjusting a phase of the data signal; a clock output circuit outputting first to fourth clock signals to a plurality of clock pads of the plurality of pads and including first to fourth clock delay cells adjusting phases of the first to fourth clock signals; and a controller adjusting a delay amount of at least one of the first to fourth clock delay cells and the data delay cell so that each of the first to fourth clock signals is aligned with the data signal in the memory device.

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