公开(公告)号：US11508733B2

公开(公告)日：2022-11-22

申请号：US16744871

申请日：2020-01-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyungjun Noh ,  Junsoo Kim ,  Dongsoo Woo ,  Namho Jeon

IPC: H01L25/065 ,  H01L25/00 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L27/108 ,  H01L29/66 ,  H01L21/285 ,  H01L21/311 ,  H01L21/3213 ,  H01L23/528 ,  H01L29/51 ,  H01L21/3115 ,  H01L21/265 ,  H01L21/28 ,  H01L21/02 ,  H01L21/3065

Abstract: An integrated circuit device includes: a substrate including active regions; a device isolation film defining the active regions; a word line arranged over the active regions and the device isolation film and extending in a first horizontal direction; and a gate dielectric film arranged between the substrate and the word line and between the device isolation film and the word line, in which, in a second horizontal direction orthogonal to the first horizontal direction, a width of a second portion of the word line over the device isolation film is greater than a width of a first portion of the word line over the active regions. To manufacture the integrated circuit device, an impurity region is formed in the substrate and the device isolation film by implanting dopant ions into the substrate and the device isolation film, and a thickness of a portion of the impurity region is reduced.

公开(公告)号：US20240023311A1

公开(公告)日：2024-01-18

申请号：US18178401

申请日：2023-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangho Lee ,  Moonyoung Jeong ,  Hyungjun Noh

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/482 ,  H10B12/05

Abstract: A semiconductor device includes a vertical pattern including a first source/drain region, a second source/drain region having a height higher than a height of the first source/drain region, and a vertical channel region between the first and second source/drain regions, a gate structure facing a first side surface of the vertical pattern, and a back gate structure facing a second side surface, opposite to the first side surface of the vertical pattern. The gate structure includes a gate electrode on the first side surface of the vertical pattern, and a gate dielectric layer including a portion disposed between the vertical pattern and the gate electrode. The back gate structure includes a back gate electrode on the second side surface of the vertical pattern, and a dielectric structure including a portion disposed between the vertical pattern and the back gate electrode. The dielectric structure includes an air gap.

公开(公告)号：US20230320077A1

公开(公告)日：2023-10-05

申请号：US18187229

申请日：2023-03-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moonyoung Jeong ,  Kiseok Lee ,  Sangho Lee ,  Hyungjun Noh

IPC: H10B12/00 ,  H01L23/528

CPC classification number: H10B12/36 ,  H10B12/482 ,  H10B12/488 ,  H01L23/5283 ,  H10B12/485

Abstract: A semiconductor device includes a substrate, a first gate structure and a second gate structure on the substrate, a single back gate structure between the first gate structure and the second gate structure, a first structure including a first vertical channel region extending in a vertical direction, at least a portion of the first vertical channel region between the first gate structure and the single back gate structure, and a second structure including a second vertical channel region extending in the vertical direction. The second structure is spaced apart from the first structure, and at least a portion of the second vertical channel region is between the second gate structure and the single back gate structure.