公开(公告)号：US20240292594A1

公开(公告)日：2024-08-29

申请号：US18384407

申请日：2023-10-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SangHyun LEE ,  Kiseok LEE ,  Seokhan PARK ,  Sung-Min PARK ,  Iljae SHIN ,  Dongjun LEE ,  Jinwoo HAN

IPC: H10B12/00

CPC classification number: H10B12/30 ,  H10B12/05 ,  H10B12/50

Abstract: A semiconductor memory device includes a semiconductor substrate; a stack structure that includes word lines and interlayer dielectric patterns that are alternately stacked on the semiconductor substrate; an etch stop layer on the stack structure; semiconductor patterns that penetrate the word lines; a bit line in contact with the semiconductor patterns; capping dielectric patterns between the bit line and the word lines, the capping dielectric patterns covering sidewalls of the word lines; and a data storage element on the semiconductor substrate, wherein a level of a bottom surface of the etch stop layer is the same as a level of a top surface of the data storage element.

公开(公告)号：US20210125989A1

公开(公告)日：2021-04-29

申请号：US16986367

申请日：2020-08-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joongchan SHIN ,  Changkyu KIM ,  Hui-Jung KIM ,  Iljae SHIN ,  Taehyun AN ,  Kiseok LEE ,  Eunju CHO ,  Hyungeun CHOI ,  Sung-Min PARK ,  Ahram LEE ,  Sangyeon HAN ,  Yoosang HWANG

IPC: H01L27/108 ,  H01L23/528

Abstract: A three-dimensional semiconductor memory device includes first semiconductor patterns, which are vertically spaced apart from each other on a substrate, each of which includes first and second end portions spaced apart from each other, and first and second side surfaces spaced apart from each other to connect the first and second end portions, first and second source/drain regions disposed in each of the first semiconductor patterns and adjacent to the first and second end portions, respectively, a channel region in each of the first semiconductor patterns and between the first and second source/drain regions, a first word line adjacent to the first side surfaces and the channel regions and vertically extended, and a gate insulating layer interposed between the first word line and the first side surfaces. The gate insulating layer may be extended to be interposed between the first source/drain regions.