公开(公告)号：US20210043629A1

公开(公告)日：2021-02-11

申请号：US16880230

申请日：2020-05-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hui-Jung KIM ,  Taehyun AN ,  Kiseok LEE ,  Keunnam KIM ,  Yoosang HWANG

IPC: H01L27/108 ,  G11C5/06

Abstract: A semiconductor memory device includes a stack including a plurality of layers vertically stacked on a substrate, each of the layers including a bit line extending in a first direction and a semiconductor pattern extending from the bit line in a second direction crossing the first direction, a gate electrode along each of the semiconductor patterns stacked, a vertical insulating layer on the gate electrode, a stopper layer, and a data storing element electrically connected to each of the semiconductor patterns. The data storing element includes a first electrode electrically connected to each of the semiconductor patterns, a second electrode on the first electrode, and a dielectric layer between the first and second electrodes. The stopper layer is between the vertical insulating layer and the second electrode.

公开(公告)号：US20220173106A1

公开(公告)日：2022-06-02

申请号：US17369320

申请日：2021-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungeun CHOI ,  Kiseok LEE ,  Seungjae JUNG ,  Joongchan SHIN ,  Taehyun AN ,  Moonyoung JEONG ,  Sangyeon HAN

IPC: H01L27/108 ,  H01L29/08

Abstract: A semiconductor memory device includes: a bit line extending on a substrate in a vertical direction; a transistor body part including a first source-drain region, a monocrystalline channel layer, and a second source-drain region that are sequentially arranged in a first horizontal direction and connected to the bit line; gate electrode layers extending in a second horizontal direction that is orthogonal to the first horizontal direction, with a gate dielectric layer between the gate electrode layers and the monocrystalline channel layer, and covering upper and lower surfaces of the monocrystalline channel layer; and a cell capacitor including a lower electrode layer, a capacitor dielectric layer, and an upper electrode layer at a side of the transistor body that is opposite to the bit line in the first horizontal direction and is connected to the second source-drain region.

公开(公告)号：US20230180452A1

公开(公告)日：2023-06-08

申请号：US17956102

申请日：2022-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Taegyu KANG ,  Keunnam KIM ,  Sung-Min PARK ,  Taehyun AN ,  Sanghyun LEE ,  Eunsuk JANG ,  Moonyoung JEONG ,  Euichul JEONG ,  Hyungeun CHOI

IPC: H01L27/108 ,  G11C5/04 ,  G11C7/18 ,  G11C8/14

CPC classification number: H01L27/108 ,  G11C5/04 ,  G11C7/18 ,  G11C8/14

Abstract: A semiconductor memory device includes a word line extended parallel to a top surface of a semiconductor substrate, a channel pattern crossing the word line and having a long axis parallel to the top surface, a bit line extended perpendicular to the top surface and in contact with a first side surface of the channel pattern, and a data storage element in contact with a second side surface of the channel pattern opposite to the first side surface. The channel pattern includes a first dopant region adjacent to the bit line, a second dopant region adjacent to the data storage element, and a channel region between the first and second dopant regions and overlapped with the word line. At least one of the first and second dopant regions includes a low concentration region adjacent to the channel region, and a high concentration region spaced apart from the channel region.

公开(公告)号：US20210125989A1

公开(公告)日：2021-04-29

申请号：US16986367

申请日：2020-08-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joongchan SHIN ,  Changkyu KIM ,  Hui-Jung KIM ,  Iljae SHIN ,  Taehyun AN ,  Kiseok LEE ,  Eunju CHO ,  Hyungeun CHOI ,  Sung-Min PARK ,  Ahram LEE ,  Sangyeon HAN ,  Yoosang HWANG

IPC: H01L27/108 ,  H01L23/528

Abstract: A three-dimensional semiconductor memory device includes first semiconductor patterns, which are vertically spaced apart from each other on a substrate, each of which includes first and second end portions spaced apart from each other, and first and second side surfaces spaced apart from each other to connect the first and second end portions, first and second source/drain regions disposed in each of the first semiconductor patterns and adjacent to the first and second end portions, respectively, a channel region in each of the first semiconductor patterns and between the first and second source/drain regions, a first word line adjacent to the first side surfaces and the channel regions and vertically extended, and a gate insulating layer interposed between the first word line and the first side surfaces. The gate insulating layer may be extended to be interposed between the first source/drain regions.