公开(公告)号：US20240334673A1

公开(公告)日：2024-10-03

申请号：US18518687

申请日：2023-11-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Seok LEE ,  Hong Jun LEE ,  Hyun Geun CHOI ,  Keun Nam KIM ,  In Cheol NAM ,  Bo Won YOO ,  Jin Woo HAN

IPC: H10B12/00

CPC classification number: H10B12/038 ,  H10B12/482 ,  H10B12/488

Abstract: A semiconductor device includes a lower substrate, a memory cell structure including a wordline on the lower substrate, a bitline disposed on the lower substrate and intersecting the wordline, and a cell capacitor connected to the lower substrate, an upper substrate having a back side adjacent to the lower substrate and a front side opposite to the back side, a circuit element disposed on the front side of the upper substrate and overlapping the memory cell structure in a vertical direction, and a through via penetrating the upper substrate and electrically connecting the memory cell structure and the circuit element with each other.

公开(公告)号：US20180130806A1

公开(公告)日：2018-05-10

申请号：US15642394

申请日：2017-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： In Cheol NAM ,  Sung Hee HAN ,  Dae Sun KIM

IPC: H01L27/108 ,  H01L21/765 ,  H01L29/49 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L27/10826 ,  H01L21/765 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/10897 ,  H01L29/0646 ,  H01L29/4925 ,  H01L29/785

Abstract: A semiconductor device includes a substrate including an active region and an element isolation region defining the active region, a gate trench extending into the element isolation region and penetrating the active region, and a gate structure filling the gate trench and including a first conductivity-type semiconductor layer, a conductive layer, and a second conductivity-type semiconductor layer, sequentially stacked from a lower portion of the gate trench.

公开(公告)号：US20180166150A1

公开(公告)日：2018-06-14

申请号：US15794150

申请日：2017-10-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwang-Won LEE ,  In Cheol NAM

IPC: G11C29/44 ,  G11C29/12 ,  G11C29/00 ,  G06F12/08

CPC classification number: G11C29/4401 ,  G06F12/08 ,  G11C29/00 ,  G11C29/12 ,  G11C29/44 ,  G11C29/76 ,  G11C2029/4402

Abstract: A memory device includes a memory cell array, a comparator, and a virtual fail generator. The memory cell array includes memory cells. The comparator determines whether a fail of a first memory cell of the memory cell array corresponding to a first address is generated, by comparing data stored in the first memory cell with an expected value. The virtual fail generator generates a second address based on the first address provided from the comparator, in response to the comparator determining that the fail of the first memory cell is generated. The first memory cell and a second memory cell corresponding to the second address are repaired by spare memory cells in response to a repair command.