公开(公告)号：US20180040549A1

公开(公告)日：2018-02-08

申请号：US15485794

申请日：2017-04-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JONG-BO SHIM ,  SANG-UK HAN ,  YUN-SEOK CHOI ,  JI-HWANG KIM

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3185 ,  H01L23/49822 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16157

Abstract: A printed circuit board (PCB) includes a substrate base including at least two chip attach regions spaced apart from one another, a plurality of upper pads disposed in the at least two chip attach regions of the substrate base, an accommodation cavity overlapping a part of each of the at least two chip attach regions and recessed in an upper surface of the substrate base, and at least one spacing groove recessed in the upper surface of the substrate base. The at least one spacing groove is connected to the accommodation cavity, and extends in a region between the at least two chip attach regions.

公开(公告)号：US20180294216A1

公开(公告)日：2018-10-11

申请号：US16004539

申请日：2018-06-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JI-HWANG KIM ,  JONG-BO SHIM ,  CHA-JEA JO ,  WON-IL LEE

IPC: H01L23/498 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00

CPC classification number: H01L23/49838 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49827 ,  H01L24/09 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06586

Abstract: A semiconductor package includes a substrate, a rewiring layer, a plurality of semiconductor chip stack structures, and a second semiconductor chip. The rewiring layer is disposed on an upper surface of the substrate. The rewiring layer includes a concave portion. The semiconductor chip stack structures include a plurality of first semiconductor chips. The first semiconductor chips are disposed on the rewiring layer. The first semiconductor chips are spaced apart from each other in a horizontal direction. The second semiconductor chip is disposed within the concave portion. The second semiconductor chip is configured to electrically connect each of the plurality of semiconductor chip stack structures to each other.