公开(公告)号：US20160225721A1

公开(公告)日：2016-08-04

申请号：US14957741

申请日：2015-12-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： EUN-KYOUNG CHOI ,  SANG-UK HAN ,  CHA-JEA JO ,  TAE-JE CHO

IPC: H01L23/544 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/544 ,  H01L21/563 ,  H01L23/31 ,  H01L23/3128 ,  H01L24/00 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2223/54406 ,  H01L2223/54413 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2224/32245 ,  H01L2224/48247

Abstract: A semiconductor package having an upper surface, a lower surface, and at least one side surface is provided. The semiconductor package includes a mold member disposed on the upper surface and at least one side surface of a semiconductor chip included in the semiconductor package. A marking pattern in the semiconductor package having information about the semiconductor chip is formed on at least one side surface of the mold member.

Abstract translation: 提供具有上表面，下表面和至少一个侧表面的半导体封装。 半导体封装包括设置在半导体封装中包括的半导体芯片的上表面和至少一个侧表面上的模具构件。 具有关于半导体芯片的信息的半导体封装中的标记图案形成在模具构件的至少一个侧表面上。

公开(公告)号：US20180061812A1

公开(公告)日：2018-03-01

申请号：US15499229

申请日：2017-04-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： WON-IL LEE ,  CHA-JEA JO ,  JI-HWANG KIM

IPC: H01L25/065 ,  H01L23/00 ,  H01L21/56 ,  H01L21/683 ,  H01L21/48 ,  H01L23/31 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/19 ,  H01L24/81 ,  H01L24/97 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05025 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05169 ,  H01L2224/05184 ,  H01L2224/06181 ,  H01L2224/11002 ,  H01L2224/12105 ,  H01L2224/14181 ,  H01L2224/16113 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/81005 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06586 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1443 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2224/81

Abstract: Methods of manufacturing a semiconductor package are provided. The methods may include manufacturing a semiconductor chip in a first semiconductor manufacturing environment and mounting the semiconductor chip on an upper surface of a printed circuit board. The method may also include forming a molding member in a second semiconductor manufacturing environment that is different from the first semiconductor manufacturing environment, forming a capping member including a material different from the molding member and covering an exposed outer surface of the molding member, and attaching a carrier substrate onto the capping member. The semiconductor chip may be between the printed circuit board and the carrier substrate. The method may further include forming a redistribution line layer on a lower surface of the printed circuit board in a third semiconductor manufacturing environment, forming an external connection member on the redistribution line layer, and removing the carrier substrate.

公开(公告)号：US20170236798A1

公开(公告)日：2017-08-17

申请号：US15349327

申请日：2016-11-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： GUN-AH LEE ,  Jl-HWAN HWANG ,  CHA-JEA JO ,  DONG-HAN KIM ,  SEUNG-KON MOK

IPC: H01L23/00 ,  H01L21/683 ,  H01L21/67

CPC classification number: H01L21/6838 ,  H01L21/67144 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/75702 ,  H01L2224/75901 ,  H01L2224/7592 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2225/06513 ,  H01L2924/07802 ,  H01L2924/1434 ,  H01L2924/15174 ,  H01L2924/37001 ,  H01L2924/00012 ,  H01L2924/00

Abstract: An apparatus for stacking semiconductor chips includes a push member configured to apply pressure to a semiconductor chip disposed on a substrate. The push member includes a push plate configured to contact the semiconductor chip, and a push rod connected to the push plate. The push plate includes a central portion having an area smaller than an area of an upper side of the semiconductor chip, and a plurality of protrusions disposed at respective ends of the central portion.

公开(公告)号：US20140273350A1

公开(公告)日：2014-09-18

申请号：US14088576

申请日：2013-11-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： BYOUNG-SOO KWAK ,  CHA-JEA JO ,  TAE-JE CHO ,  SANG-UK HAN

IPC: H01L25/00

CPC classification number: H01L25/50 ,  H01L25/0657 ,  H01L2224/13 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a method of fabricating a multi-chip stack package. The method includes preparing single-bodied lower chips having a single-bodied lower chip substrate having a first surface and a second surface disposed opposite the first surface, bonding unit package substrates onto the first surface of the single-bodied lower chip substrate to form a single-bodied substrate-chip bonding structure, separating the single-bodied substrate-chip bonding structure into a plurality of unit substrate-chip bonding structures, preparing single-bodied upper chips having a single-bodied upper chip substrate, bonding the plurality of unit substrate-chip bonding structures onto a first surface of the single-bodied upper chip substrate to form a single-bodied semiconductor chip stack structure, and separating the single-bodied semiconductor chip stack structure into a plurality of unit semiconductor chip stack structures.

Abstract translation: 提供一种制造多芯片堆叠封装的方法。 该方法包括制备具有单体下部芯片衬底的单体下部芯片，其具有第一表面和与第一表面相对设置的第二表面，将单元封装衬底粘合到单体下部芯片衬底的第一表面上以形成 单体衬底芯片接合结构，将单体衬底 - 芯片接合结构分离成多个单元衬底 - 芯片接合结构，制备具有单体上片状衬底的单体上片，将多个单元 衬底 - 芯片接合结构到单体上芯片衬底的第一表面上以形成单体半导体芯片堆叠结构，并将单体半导体芯片堆叠结构分离成多个单元半导体芯片堆栈结构。

公开(公告)号：US20180294216A1

公开(公告)日：2018-10-11

申请号：US16004539

申请日：2018-06-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JI-HWANG KIM ,  JONG-BO SHIM ,  CHA-JEA JO ,  WON-IL LEE

IPC: H01L23/498 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00

CPC classification number: H01L23/49838 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49827 ,  H01L24/09 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06586

Abstract: A semiconductor package includes a substrate, a rewiring layer, a plurality of semiconductor chip stack structures, and a second semiconductor chip. The rewiring layer is disposed on an upper surface of the substrate. The rewiring layer includes a concave portion. The semiconductor chip stack structures include a plurality of first semiconductor chips. The first semiconductor chips are disposed on the rewiring layer. The first semiconductor chips are spaced apart from each other in a horizontal direction. The second semiconductor chip is disposed within the concave portion. The second semiconductor chip is configured to electrically connect each of the plurality of semiconductor chip stack structures to each other.