公开(公告)号：US20180040549A1

公开(公告)日：2018-02-08

申请号：US15485794

申请日：2017-04-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JONG-BO SHIM ,  SANG-UK HAN ,  YUN-SEOK CHOI ,  JI-HWANG KIM

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3185 ,  H01L23/49822 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16157

Abstract: A printed circuit board (PCB) includes a substrate base including at least two chip attach regions spaced apart from one another, a plurality of upper pads disposed in the at least two chip attach regions of the substrate base, an accommodation cavity overlapping a part of each of the at least two chip attach regions and recessed in an upper surface of the substrate base, and at least one spacing groove recessed in the upper surface of the substrate base. The at least one spacing groove is connected to the accommodation cavity, and extends in a region between the at least two chip attach regions.

公开(公告)号：US20140175679A1

公开(公告)日：2014-06-26

申请号：US14190079

申请日：2014-02-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： HEUNG-KYU KWON ,  SEONG-HO SHIN ,  YUN-SEOK CHOI ,  YONG-HOON KIM

IPC: H01L23/00

CPC classification number: H01L24/06 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49866 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48227 ,  H01L2224/48229 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A package stack structure may an upper package include an upper package substrate having a first edge and a second edge opposite to the first edge. The upper package substrate has a first region arranged near the first edge and a second region arranged near the second edge. A first upper semiconductor device is mounted on the upper package substrate. The package stack structure may also include a lower package having a lower package substrate and a lower semiconductor device. The lower package is connected to the upper package through a plurality of inter-package connectors. The plurality of the inter-package connectors may include first inter-package connectors configured to transmit data signals; second inter-package connectors configured to transmit address/control signals; third inter-package connectors configured to provide a supply voltage for an address/control circuit; and fourth inter-package connectors configured to provide a supply voltage for a data circuit.

Abstract translation: 封装堆叠结构可以是上封装包括具有第一边缘和与第一边缘相对的第二边缘的上封装基板。 上封装衬底具有布置在第一边缘附近的第一区域和布置在第二边缘附近的第二区域。 第一上半导体器件安装在上封装衬底上。 封装堆叠结构还可以包括具有下封装衬底和下半导体器件的下封装。 下封装通过多个封装间连接器连接到上封装。 多个包装间连接器可以包括被配置为传送数据信号的第一包装间连接器; 配置成发送地址/控制信号的第二串联连接器连接器; 第三组件间连接器，被配置为提供地址/控制电路的电源电压; 以及被配置为提供数据电路的电源电压的第四组件间连接器。