公开(公告)号：US20170016955A1

公开(公告)日：2017-01-19

申请号：US15281998

申请日：2016-09-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MIN-SU KIM ,  MATTHEW BERZINS ,  JONG-WOO KIM

IPC: G01R31/3177 ,  H03K19/21 ,  G01R31/317 ,  H03K3/037

CPC classification number: G01R31/3177 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/318541 ,  H03K3/0372 ,  H03K3/35625 ,  H03K19/21

Abstract: A multi-bit flip-flop includes a plurality of multi-bit flip-flop blocks that share a clock signal. Each of the multi-bit flip-flop blocks includes a single inverter and a plurality of flip-flops. The single inverter generates an inverted clock signal by inverting the clock signal. Each of the flip-flops includes a master latch part and a slave latch part and operates the master latch part and the slave latch part based on the clock signal and the inverted clock signal. Here, the flip-flops are triggered at rising edges of the clock signal. Thus, the multi-bit flip-flop operating as a master-slave flip-flop may minimize (or, reduce) power consumption occurring in a clock path through which the clock signal is transmitted.

Abstract translation: 多位触发器包括共享时钟信号的多个多位触发器块。 多位触发器块中的每一个包括单个反相器和多个触发器。 单个反相器通过反相时钟信号产生反相时钟信号。 每个触发器包括主锁存部分和从锁存器部分，并且基于时钟信号和反相时钟信号操作主锁存器部分和从锁存器部分。 这里，触发器在时钟信号的上升沿被触发。 因此，作为主从触发器操作的多位触发器可以最小化（或降低）发送时钟信号的时钟通路中发生的功耗。

公开(公告)号：US20190109151A1

公开(公告)日：2019-04-11

申请号：US16211496

申请日：2018-12-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JU-HYUN KANG ,  HYUN LEE ,  MIN-SU KIM ,  JI-KYUM KIM ,  JONG-WOO KIM

IPC: H01L27/118 ,  G06F17/50

CPC classification number: H01L27/11807 ,  G06F17/505 ,  H01L2027/11875 ,  H01L2027/11881

Abstract: An integrated circuit includes a complex logic cell. The complex logic cell includes a first logic circuit providing a first output signal from a first input signal group and a common input signal group, and a second logic circuit providing a second output signal from a second input signal group and the common input signal group. The first and second logic circuits respectively include first and second transistors formed from a gate electrode, the gate electrode extending in a first direction and receiving a first common input signal of the common input signal group.

公开(公告)号：US20170317100A1

公开(公告)日：2017-11-02

申请号：US15409674

申请日：2017-01-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JU-HYUN KANG ,  HYUN LEE ,  MIN-SU KIM ,  JI-KYUM KIM ,  JONG-WOO KIM

IPC: H01L27/118 ,  G06F17/50

CPC classification number: H01L27/11807 ,  G06F17/505 ,  H01L2027/11875 ,  H01L2027/11881

Abstract: An integrated circuit includes a complex logic cell. The complex logic cell includes a first logic circuit providing a first output signal from a first input signal group and a common input signal group, and a second logic circuit providing a second output signal from a second input signal group and the common input signal group. The first and second logic circuits respectively include first and second transistors formed from a gate electrode, the gate electrode extending in a first direction and receiving a first common input signal of the common input signal group.