公开(公告)号：US20200235119A1

公开(公告)日：2020-07-23

申请号：US16844064

申请日：2020-04-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoo-cheol SHIN ,  Young-woo PARK ,  Jae-duk LEE

IPC: H01L27/11578 ,  H01L27/11526 ,  H01L27/11573 ,  H01L27/11551 ,  H01L27/11556 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  H01L27/11582 ,  H01L27/1157

Abstract: A semiconductor device includes a peripheral circuit region on a substrate, a polysilicon layer on the peripheral circuit region, a memory cell array region on the polysilicon layer and overlapping the peripheral circuit region, the peripheral circuit region being under the memory cell array region, an upper interconnection layer on the memory cell array region, and a vertical contact through the memory cell array region and the polysilicon layer, the vertical contact connecting the upper interconnection layer to the peripheral circuit region.

公开(公告)号：US20210175244A1

公开(公告)日：2021-06-10

申请号：US17155441

申请日：2021-01-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoo-cheol SHIN ,  Young-woo PARK ,  Jae-duk LEE

IPC: H01L27/11578 ,  H01L27/11526 ,  H01L27/11573 ,  H01L29/66 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/788 ,  H01L27/11551 ,  H01L29/792 ,  H01L27/11582

Abstract: A semiconductor device includes a peripheral circuit region on a substrate, a polysilicon layer on the peripheral circuit region, a memory cell array region on the polysilicon layer and overlapping the peripheral circuit region, the peripheral circuit region being under the memory cell array region, an upper interconnection layer on the memory cell array region, and a vertical contact through the memory cell array region and the polysilicon layer, the vertical contact connecting the upper interconnection layer to the peripheral circuit region.

公开(公告)号：US20200091176A1

公开(公告)日：2020-03-19

申请号：US16288449

申请日：2019-02-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jang-gn YUN ,  Jae-duk LEE

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L21/28 ,  H01L21/768 ,  H01L21/02 ,  H01L29/792 ,  H01L29/66

Abstract: An integrated circuit device includes word line structures, insulating structures, a channel hole, and charge trap patterns. The word line structures and the insulating structures are interleaved with each other and extend in a horizontal direction parallel to a main surface of a substrate, and overlap one another in a vertical direction. The channel hole passes through the word line structures and the insulating structures in the vertical direction. The charge trap patterns are located in the channel hole, and are spaced apart from one another in the vertical direction with a local insulating region therebetween.

公开(公告)号：US20160155751A1

公开(公告)日：2016-06-02

申请号：US15018477

申请日：2016-02-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoo-cheol SHIN ,  Young-woo PARK ,  Jae-duk LEE

IPC: H01L27/115

CPC classification number: H01L27/11578 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

Abstract: A semiconductor device includes a peripheral circuit region on a substrate, a polysilicon layer on the peripheral circuit region, a memory cell array region on the polysilicon layer and overlapping the peripheral circuit region, the peripheral circuit region being under the memory cell array region, an upper interconnection layer on the memory cell array region, and a vertical contact through the memory cell array region and the polysilicon layer, the vertical contact connecting the upper interconnection layer to the peripheral circuit region.

公开(公告)号：US20180138192A1

公开(公告)日：2018-05-17

申请号：US15869888

申请日：2018-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoo-cheol SHIN ,  Young-woo PARK ,  Jae-duk LEE

IPC: H01L27/11578 ,  H01L27/1157 ,  H01L29/792 ,  H01L29/788 ,  H01L29/66 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/11582

CPC classification number: H01L27/11578 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

Abstract: A semiconductor device includes a peripheral circuit region on a substrate, a polysilicon layer on the peripheral circuit region, a memory cell array region on the polysilicon layer and overlapping the peripheral circuit region, the peripheral circuit region being under the memory cell array region, an upper interconnection layer on the memory cell array region, and a vertical contact through the memory cell array region and the polysilicon layer, the vertical contact connecting the upper interconnection layer to the peripheral circuit region.