公开(公告)号：US20210391259A1

公开(公告)日：2021-12-16

申请号：US17129083

申请日：2020-12-21

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jiyoung Ahn ,  Seunguk Han ,  Sunghwan Kim ,  Seoryong Park ,  Kiseok Lee ,  Yoonyoung Choi ,  Taehee Han ,  Jiseok Hong

IPC分类号： H01L23/528

摘要： An integrated circuit device is provided. The integrated circuit device includes: a bit line on a substrate, the bit line including a lower conductive layer and an upper conductive layer; an insulating capping pattern on the bit line; and a main insulating spacer on a sidewall of the bit line and a sidewall of the insulating capping pattern, the main insulating spacer including an extended portion that is convex toward the upper conductive layer.

公开(公告)号：US11908797B2

公开(公告)日：2024-02-20

申请号：US17129083

申请日：2020-12-21

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jiyoung Ahn ,  Seunguk Han ,  Sunghwan Kim ,  Seoryong Park ,  Kiseok Lee ,  Yoonyoung Choi ,  Taehee Han ,  Jiseok Hong

IPC分类号： H01L23/528 ,  H01L29/06 ,  H10B12/00 ,  H01L23/522 ,  H01L21/768 ,  H01L21/764

CPC分类号： H01L23/5283 ,  H01L21/764 ,  H01L21/7682 ,  H01L29/0649 ,  H10B12/482 ,  H10B12/485 ,  H10B12/488 ,  H01L23/5222 ,  H10B12/0335 ,  H10B12/315 ,  H10B12/34

摘要： An integrated circuit device is provided. The integrated circuit device includes: a bit line on a substrate, the bit line including a lower conductive layer and an upper conductive layer; an insulating capping pattern on the bit line; and a main insulating spacer on a sidewall of the bit line and a sidewall of the insulating capping pattern, the main insulating spacer including an extended portion that is convex toward the upper conductive layer.

公开(公告)号：US11647627B2

公开(公告)日：2023-05-09

申请号：US17168952

申请日：2021-02-05

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jiseok Hong ,  Sangho Lee ,  Seoryong Park ,  Jiyoung Ahn ,  Kiseok Lee ,  Kiseok Lee ,  Yoonyoung Choi ,  Seunguk Han

IPC分类号： H01L27/108

CPC分类号： H01L27/10888 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885

摘要： An integrated circuit device includes: a substrate including a plurality of active regions; a bit line extending on the substrate in a horizontal direction; a direct contact connected between a first active region selected among the plurality of active regions and the bit line; an inner oxide layer contacting a sidewall of the direct contact; and a carbon-containing oxide layer nonlinearly extending on a sidewall of the bit line in a vertical direction, the carbon-containing oxide layer contacting the sidewall of the bit line.

公开(公告)号：US20210398569A1

公开(公告)日：2021-12-23

申请号：US17168952

申请日：2021-02-05

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jiseok Hong ,  Sangho Lee ,  Seoryong Park ,  Jiyoung Ahn ,  Kiseok Lee ,  Kiseok Lee ,  Yoonyoung Choi ,  Seunguk Han

IPC分类号： G11C5/06 ,  H01L27/108

摘要： An integrated circuit device includes: a substrate including a plurality of active regions; a bit line extending on the substrate in a horizontal direction; a direct contact connected between a first active region selected among the plurality of active regions and the bit line; an inner oxide layer contacting a sidewall of the direct contact; and a carbon-containing oxide layer nonlinearly extending on a sidewall of the bit line in a vertical direction, the carbon-containing oxide layer contacting the sidewall of the bit line.

公开(公告)号：US20230232616A1

公开(公告)日：2023-07-20

申请号：US18186593

申请日：2023-03-20

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jiseok HONG ,  Sangho Lee ,  Seoryong Park ,  Jiyoung Ahn ,  Kiseok Lee ,  Kiseok Lee ,  Yoonyoung Choi ,  Seunguk Han

IPC分类号： H10B12/00

CPC分类号： H10B12/485 ,  H10B12/315 ,  H10B12/0335 ,  H10B12/482

摘要： An integrated circuit device includes: a substrate including a plurality of active regions; a bit line extending on the substrate in a horizontal direction; a direct contact connected between a first active region selected among the plurality of active regions and the bit line; an inner oxide layer contacting a sidewall of the direct contact; and a carbon-containing oxide layer nonlinearly extending on a sidewall of the bit line in a vertical direction, the carbon-containing oxide layer contacting the sidewall of the bit line.

公开(公告)号：US11557596B2

公开(公告)日：2023-01-17

申请号：US17192086

申请日：2021-03-04

申请人： Samsung Electronics Co., Ltd.

发明人： Seoryong Park ,  Seunguk Han ,  Jiyoung Ahn ,  Kiseok Lee ,  Yoonyoung Choi ,  Jiseok Hong

IPC分类号： H01L27/11551 ,  H01L27/11519 ,  G11C8/14 ,  H01L27/11578 ,  G11C7/18 ,  H01L27/11565

摘要： A semiconductor memory device includes a substrate with a cell array region, a first interface region, and a second interface region, the cell array region being provided with active regions, bit lines on the cell array region and the second interface region, dielectric patterns on top surfaces of the bit lines and extending along the top surfaces of the bit lines and further extending onto the first interface region, a device isolation pattern on the substrate, and including a first portion on the cell array region and a second portion on the first interface region, the first portion defining the active regions, the second portion being provided with first recesses, and each first recess being disposed between two adjacent dielectric patterns, and first sacrificial semiconductor patterns disposed on the first interface region and in the first recesses. The first sacrificial semiconductor patterns include polycrystalline silicon.