公开(公告)号：US20250132764A1

公开(公告)日：2025-04-24

申请号：US18884601

申请日：2024-09-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Pillseong KANG ,  Chulho KIM ,  Sangmin YOO ,  Sangho LEE ,  Joonhee LEE ,  Ikkyun JO

IPC: H03L7/099 ,  H03B5/12

Abstract: A phase-locked loop (PLL) circuit comprising an oscillator including a first and a second capacitor cell array, each including a plurality of capacitor cells, and a control logic circuit connected to the oscillator. The control logic circuit configured to generate control code configured to control the oscillator such that the oscillator is configured to output a signal with a target frequency, the control code generated based on a first frequency of a first signal output from the oscillator and the target frequency, control at least some of capacitor cells included in the first capacitor cell array based on a first partial code generated based on a specified number of bits of the control code, and control at least some of capacitor cells included in the second capacitor cell array based on a second partial code generated based on bits other than the specified number of bits of the control code.

公开(公告)号：US20230081373A1

公开(公告)日：2023-03-16

申请号：US17829011

申请日：2022-05-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bosuk KANG ,  Joonhee LEE ,  Seonghun JEONG

IPC: H01L27/11575 ,  H01L27/11556 ,  H01L27/11548 ,  H01L27/11582

Abstract: A semiconductor device includes a substrate having a first region and a second region, gate electrodes spaced apart from each other in a first direction, perpendicular to an upper surface of the substrate, and extend in a second direction, and have different lengths on the second region, channel structures that penetrate the gate electrodes, extend in the first direction, and respectively include a channel layer on the first region, support structures that penetrate the gate electrodes and extend in the first direction on the second region, and a separation region that penetrates the gate electrodes and extend in the second direction. The substrate has a recess region that overlaps the separation region in the first direction and extends downward from an upper surface in the second region, adjacent to the first region. The separation region has a protrusion that protrudes downward to correspond to the recess region.

公开(公告)号：US20250080124A1

公开(公告)日：2025-03-06

申请号：US18809865

申请日：2024-08-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Pillseong KANG ,  Chulho KIM ,  Sangho LEE ,  Joonhee LEE ,  Ikkyun JO

IPC: H03L7/099 ,  H03L7/093

Abstract: A phase-locked loop circuit includes an oscillator including a plurality of capacitor cells, and a control logic circuit that receives an output from the oscillator. The control logic circuit compares a target frequency with a first frequency of a first signal output from the oscillator, generates a first input code to control at least a portion of the plurality of capacitor cells to output a signal having the target frequency based on the comparison, generates a first output code corresponding to the first input code when the first input code is within a predetermined range of input codes, and controls at least two capacitor cells from among the plurality of capacitor cells based on the first output code. The oscillator may output a second signal having a second frequency through an electrical path including capacitor cells other than grounded capacitor cells from among the plurality of capacitor cells.

公开(公告)号：US20220077864A1

公开(公告)日：2022-03-10

申请号：US17334077

申请日：2021-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinwoong KIM ,  Myounggyun KIM ,  Joonhee LEE ,  Sangwook HAN

IPC: H03L7/099 ,  H03L7/093

Abstract: An electronic device includes a phase locked loop configured to perform a two-point modulation operation on a data signal by using first and second modulation paths, and the phase locked loop is configured to generate, based on a differential value of a first phase error signal generated in the first modulation path, a gain for adjusting a frequency variation of the data signal through the second modulation path so as to match with the frequency variation of the data signal through the first modulation path.

公开(公告)号：US20170026041A1

公开(公告)日：2017-01-26

申请号：US15211459

申请日：2016-07-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangwook HAN ,  Thomas Byunghak CHO ,  Jaehyun LIM ,  Sung-Jun LEE ,  Joonhee LEE ,  Jongwon CHOI

IPC: H03K19/0175 ,  H01L27/02

CPC classification number: H03K19/017509 ,  H01L27/0248

Abstract: An integrated circuit (IC), a method of testing the IC, and a method of manufacturing the IC are provided. The IC includes analog circuitry, digital circuitry, at least one first connector, and a switching unit operatively coupled with the at least one first connector and configured to, if a first signal is received, couple the analog circuitry and the at least one first connector, and, if a second signal is received, couple the digital circuitry and the at least one first connector.

Abstract translation: 提供集成电路（IC），IC的测试方法以及IC的制造方法。 所述IC包括模拟电路，数字电路，至少一个第一连接器以及与所述至少一个第一连接器可操作耦合的开关单元，并且被配置为如果接收到第一信号则将所述模拟电路和所述至少一个第一连接器 并且如果接收到第二信号，则耦合数字电路和至少一个第一连接器。