公开(公告)号：US11411078B2

公开(公告)日：2022-08-09

申请号：US16701427

申请日：2019-12-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyojoon Ryu ,  Kiyoon Kang ,  Seogoo Kang ,  Shinhwan Kang ,  Jesuk Moon ,  Byunggon Park ,  Jaeryong Sim ,  Jinsoo Lim ,  Jisung Cheon ,  Jeehoon Han

IPC: H01L27/11565 ,  H01L27/11582 ,  H01L29/06 ,  H01L23/31 ,  G11C5/06 ,  H01L27/1157 ,  H01L27/11573

Abstract: A semiconductor device including a substrate having a cell, peripheral, and boundary area; a stack structure on the cell area and including insulating and interconnection layers that are alternately stacked; a molding layer on the peripheral area boundary areas; a selection line isolation pattern extending into the stack structure; a cell channel structure passing through the stack structure; and first dummy patterns extending into the molding layer on the peripheral area, wherein upper surfaces of the first dummy patterns, an upper surface of the selection line isolation pattern, and an upper surface of the cell channel structure are coplanar, and at least one of the first dummy patterns extends in parallel with the selection line isolation pattern or cell channel structure from upper surfaces of the first dummy patterns, the upper surface of the selection line isolation pattern, and the upper surface of the cell channel structure toward the substrate.

公开(公告)号：US20210151452A1

公开(公告)日：2021-05-20

申请号：US16903990

申请日：2020-06-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jisung Cheon ,  Kiyoon Kang

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L29/792 ,  G11C5/02 ,  G11C5/06

Abstract: A memory device may include a substrate; a first stack structure comprising a plurality of first gate layers and a plurality of first interlayer insulating layers alternately stacked on the substrate; a second stack structure comprising a plurality of second gate layers and a plurality of second interlayer insulating layers alternately stacked on the first stack structure; and a channel structure penetrating the first stack structure and the second stack structure, wherein the channel structure comprises a first portion in a first channel hole penetrating the first stack structure, a second portion in a second channel hole penetrating the second stack structure, and a first protrusion located in a first recess recessed into one layer of the plurality of first interlayer insulating layers from a side portion of the first channel hole.

公开(公告)号：US11508744B2

公开(公告)日：2022-11-22

申请号：US16903990

申请日：2020-06-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jisung Cheon ,  Kiyoon Kang

IPC: H01L27/11556 ,  G11C5/02 ,  G11C5/06 ,  H01L27/11582 ,  H01L29/792

Abstract: A memory device may include a substrate; a first stack structure comprising a plurality of first gate layers and a plurality of first interlayer insulating layers alternately stacked on the substrate; a second stack structure comprising a plurality of second gate layers and a plurality of second interlayer insulating layers alternately stacked on the first stack structure; and a channel structure penetrating the first stack structure and the second stack structure, wherein the channel structure comprises a first portion in a first channel hole penetrating the first stack structure, a second portion in a second channel hole penetrating the second stack structure, and a first protrusion located in a first recess recessed into one layer of the plurality of first interlayer insulating layers from a side portion of the first channel hole.