公开(公告)号：US11114461B2

公开(公告)日：2021-09-07

申请号：US16700059

申请日：2019-12-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongseon Ahn ,  Jaeryong Sim ,  Giyong Chung ,  Jeehoon Han

IPC: H01L27/11524 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11529 ,  H01L23/60 ,  H01L27/11573 ,  H01L29/06 ,  H01L21/311 ,  H01L27/1157

Abstract: A three-dimensional (3D) semiconductor memory device including: first and second semiconductor layers horizontally spaced apart from each other; a buried insulating layer between the first and second semiconductor lavers; a first cell array structure disposed on the first semiconductor layer, and a second cell array structure disposed on the second semiconductor layer; and an isolation structure disposed on the buried insulating layer between the first and second cell array structures, wherein the first cell array structure includes: an electrode structure including electrodes, which are stacked in a direction perpendicular to a top surface of the first semiconductor layer; and a first source structure disposed between the first semiconductor layer and the electrode structure, the first source structure is extended onto the buried insulating layer, and the isolation structure is between the first source structure of the first cell array structure and a second source structure of the second cell array structure.

公开(公告)号：US12114504B2

公开(公告)日：2024-10-08

申请号：US17321747

申请日：2021-05-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungyoon Kim ,  Jaeryong Sim ,  Jeehoon Han

IPC: H10B43/50 ,  H01L21/768 ,  H01L23/535 ,  H10B41/27 ,  H10B41/41 ,  H10B41/50 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B43/50 ,  H01L21/76805 ,  H01L21/76895 ,  H01L23/535 ,  H10B41/27 ,  H10B41/41 ,  H10B41/50 ,  H10B43/27 ,  H10B43/40

Abstract: An integrated circuit device includes a substrate, a peripheral circuit structure disposed on the substrate, the peripheral circuit structure including a peripheral circuit and a lower wiring connected to the peripheral circuit, a conductive plate covering a portion of the peripheral circuit structure, a cell array structure disposed on the peripheral circuit structure with the conductive plate therebetween, the cell array structure including a memory cell array and an insulation layer surrounding the memory cell array, a through hole via passing through the insulation layer in a direction vertical to a top surface of the substrate to be connected to the lower wiring, and an etch guide member disposed in the insulation layer at the same level as the conductive plate to contact a portion of the through hole via.

公开(公告)号：US11616078B2

公开(公告)日：2023-03-28

申请号：US17406245

申请日：2021-08-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongseon Ahn ,  Jaeryong Sim ,  Giyong Chung ,  Jeehoon Han

IPC: H01L27/11524 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11529 ,  H01L23/60 ,  H01L27/11573 ,  H01L29/06 ,  H01L21/311 ,  H01L27/1157

Abstract: A three-dimensional (3D) semiconductor memory device including: first and second semiconductor layers horizontally spaced apart from each other; a buried insulating layer between the first and second semiconductor layers; a first cell array structure disposed on the first semiconductor layer, and a second cell array structure disposed on the second semiconductor layer; and an isolation structure disposed on the buried insulating layer between the first and second cell array structures, wherein the first cell array structure includes: an electrode structure including electrodes, which are stacked in a direction perpendicular to a top surface of the first semiconductor layer; and a first source structure disposed between the first semiconductor layer and the electrode structure, the first source structure is extended onto the buried insulating layer, and the isolation structure is between the first source structure of the first cell array structure and a second source structure of the second cell array structure.

公开(公告)号：US20240357825A1

公开(公告)日：2024-10-24

申请号：US18760980

申请日：2024-07-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeryong Sim ,  Shinhwan Kang ,  Jeehoon Han

IPC: H10B43/50 ,  H01L23/48 ,  H10B43/27

CPC classification number: H10B43/50 ,  H01L23/481 ,  H10B43/27

Abstract: A semiconductor device includes a lower structure including a peripheral circuit, a lower insulating structure covering the peripheral circuit, and a pattern structure on the lower insulating structure; a stack structure including interlayer insulating layers and horizontal layers alternately stacked on the lower structure, wherein the horizontal layers include gate horizontal layers in a gate region of the stack structure and first insulating horizontal layers in a first insulating region of the stack structure; a memory vertical structure including a portion penetrating the gate horizontal layers; dummy vertical structures including a portion penetrating the gate horizontal layers; a first peripheral contact plug including a portion penetrating the first insulating region; and gate contact plugs on gate pads of the gate horizontal layers, wherein upper surface of the gate contact plugs and the first peripheral contact plugs are coplanar with each other, wherein the memory vertical structure and the dummy vertical structure are contacting the pattern structure, and wherein at least one of the dummy vertical structures extend further into the pattern structure than the memory vertical structure in a downward direction.

公开(公告)号：US11411078B2

公开(公告)日：2022-08-09

申请号：US16701427

申请日：2019-12-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyojoon Ryu ,  Kiyoon Kang ,  Seogoo Kang ,  Shinhwan Kang ,  Jesuk Moon ,  Byunggon Park ,  Jaeryong Sim ,  Jinsoo Lim ,  Jisung Cheon ,  Jeehoon Han

IPC: H01L27/11565 ,  H01L27/11582 ,  H01L29/06 ,  H01L23/31 ,  G11C5/06 ,  H01L27/1157 ,  H01L27/11573

Abstract: A semiconductor device including a substrate having a cell, peripheral, and boundary area; a stack structure on the cell area and including insulating and interconnection layers that are alternately stacked; a molding layer on the peripheral area boundary areas; a selection line isolation pattern extending into the stack structure; a cell channel structure passing through the stack structure; and first dummy patterns extending into the molding layer on the peripheral area, wherein upper surfaces of the first dummy patterns, an upper surface of the selection line isolation pattern, and an upper surface of the cell channel structure are coplanar, and at least one of the first dummy patterns extends in parallel with the selection line isolation pattern or cell channel structure from upper surfaces of the first dummy patterns, the upper surface of the selection line isolation pattern, and the upper surface of the cell channel structure toward the substrate.

公开(公告)号：US12185548B2

公开(公告)日：2024-12-31

申请号：US17318306

申请日：2021-05-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Giyong Chung ,  Jaeryong Sim ,  Kwangyoung Jung ,  Jeehoon Han

IPC: H10B43/50 ,  H01L23/535 ,  H10B41/27 ,  H10B41/41 ,  H10B41/50 ,  H10B43/27 ,  H10B43/40

Abstract: A semiconductor device includes a memory cell region. The memory cell region includes a memory stack structure including a first stack structure and a second stack structure; a plurality of channel structures vertically penetrating through the memory stack structure and connected to the second substrate; at least one first dummy structure; and at least one second dummy structure. At least a portion of the first dummy structure does not overlap the second dummy structure in a vertical direction.

公开(公告)号：US12058866B2

公开(公告)日：2024-08-06

申请号：US17204248

申请日：2021-03-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeryong Sim ,  Shinhwan Kang ,  Jeehoon Han

IPC: H01L29/76 ,  H01L23/48 ,  H01L29/94 ,  H01L31/062 ,  H10B43/27 ,  H10B43/50

CPC classification number: H10B43/50 ,  H01L23/481 ,  H10B43/27

Abstract: A semiconductor device includes a lower structure including a peripheral circuit, a lower insulating structure covering the peripheral circuit, and a pattern structure on the lower insulating structure; a stack structure including interlayer insulating layers and horizontal layers alternately stacked on the lower structure, wherein the horizontal layers include gate horizontal layers in a gate region of the stack structure and first insulating horizontal layers in a first insulating region of the stack structure; a memory vertical structure including a portion penetrating the gate horizontal layers; dummy vertical structures including a portion penetrating the gate horizontal layers; a first peripheral contact plug including a portion penetrating the first insulating region; and gate contact plugs on gate pads of the gate horizontal layers, wherein upper surface of the gate contact plugs and the first peripheral contact plugs are coplanar with each other, wherein the memory vertical structure and the dummy vertical structure are contacting the pattern structure, and wherein at least one of the dummy vertical structures extend further into the pattern structure than the memory vertical structure in a downward direction.

公开(公告)号：US11844214B2

公开(公告)日：2023-12-12

申请号：US17362903

申请日：2021-06-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeryong Sim ,  Giyong Chung ,  Dongsik Oh ,  Jeehoon Han

IPC: H10B41/41 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H01L29/423 ,  H01L21/28 ,  H01L29/792 ,  H01L29/66 ,  H01L29/788

CPC classification number: H10B41/41 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42328 ,  H01L29/42344 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

Abstract: A semiconductor device includes a substrate that includes a first active region, a second active region, and an isolation region. An isolation layer pattern fills a trench in the substrate. A first gate insulation layer pattern and a first gate electrode structure are formed on the first active region. A second gate insulation layer pattern and second gate electrode structure are formed on the second active region. The first gate electrode structure includes a first polysilicon pattern, a second polysilicon pattern, and a first metal pattern. The second gate electrode structure includes a third polysilicon pattern, a fourth polysilicon pattern, and a second metal pattern. An upper surface of the isolation layer pattern is higher than upper surfaces of each of the first and third polysilicon patterns. A sidewall of each of the first and third polysilicon patterns contacts sidewalls of the isolation layer pattern.

公开(公告)号：US11515322B2

公开(公告)日：2022-11-29

申请号：US16890500

申请日：2020-06-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seogoo Kang ,  Daehyun Jang ,  Jaeryong Sim ,  Jongseon Ahn ,  Jeehoon Han

IPC: H01L27/11582 ,  H01L27/11575 ,  H01L27/11548 ,  H01L27/11556

Abstract: A semiconductor device includes a peripheral circuit region including a first substrate and circuit elements on the first substrate; and a memory cell region including a second substrate on an upper portion of the first substrate, gate electrodes spaced apart from each other and vertically stacked on the second substrate, channel structures extending vertically through the gate electrodes to the second substrate, first separation regions penetrating through the gate electrodes between the channel structures and extending in one direction, and a second separation region extending vertically to penetrate through the second substrate from above and having a bent portion due to a change in width.

公开(公告)号：US20210384220A1

公开(公告)日：2021-12-09

申请号：US17406245

申请日：2021-08-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JONGSEON AHN ,  Jaeryong Sim ,  Giyong Chung ,  Jeehoon Han

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L23/60 ,  H01L27/11573 ,  H01L29/06 ,  H01L21/311 ,  H01L27/1157

Abstract: A three-dimensional (3D) semiconductor memory device including; first and second semiconductor layers horizontally spaced apart from each other; a buried insulating layer between the first and second semiconductor layers; a first cell array structure disposed on the first semiconductor layer, and a second cell array structure disposed on the second semiconductor layer; and an isolation structure disposed on the buried insulating layer between the first and second cell array structures, wherein the first cell array structure includes: an electrode structure including electrodes, which are stacked in a direction perpendicular to a top surface of the first semiconductor layer; and a first source structure disposed between the first semiconductor layer and the electrode structure, the first source structure is extended onto the buried insulating layer, and the isolation structure is between the first source structure of the first cell array structure and a second source structure of the second cell array structure.