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1.发明授权公开(公告)号：US11824967B2
公开(公告)日：2023-11-21
申请号：US17347055
申请日：2021-06-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ju-Young Jung , Jiyoup Kim , Changkyu Seol , Pilsang Yoon , Jinsoo Lim , Myunghoon Choi
CPC classification number: H04L9/008 , H04L9/0819 , H04L9/0869 , H04L9/0894
Abstract: An electronic device includes a memory storing data from an external source, an application processing unit (APU) transmitting a secret key and public key generation command, an isolated execution environment (IEE) generating a secret key in response to the secret key generation command, generating a public key based on the secret key in response to the public key generation command, and storing the secret key, and a non-volatile memory performing write and read operations depending on a request of the APU. When the data are stored in the memory, the APU transmits a public key request to the IEE and in response the IEE transfers the public key to the APU through a mailbox protocol. The APU generates a ciphertext by performing homomorphic encryption on the data based on an encryption key in the public key, and classifies and stores the public key and the ciphertext in the non-volatile memory.
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公开(公告)号：US11672119B2
公开(公告)日：2023-06-06
申请号：US17028029
申请日：2020-09-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jisung Cheon , Jiye Noh , Byunggon Park , Jinsoo Lim
IPC: H01L29/788 , H01L27/11582 , G11C7/18 , H01L23/522 , H01L27/11565
CPC classification number: H01L27/11582 , G11C7/18 , H01L23/5226 , H01L27/11565
Abstract: A vertical memory device includes a gate electrode structure, channels, a charge storage structure, and a division pattern. The gate electrode includes gate electrodes spaced apart from each other in a first direction. The channel extends through the gate electrode structure, and includes a first portion and a second portion on and contacting the first portion. The second portion includes a lower surface having a width less than that of an upper surface of the first portion. The charge storage structure covers an outer sidewall of the channel. The division pattern extends between the channels in a second direction, and includes a first dummy channel and a first dummy charge storage structure covering a sidewall and a lower surface thereof. The first dummy channel includes the same material as that the channel, and the first dummy charge storage structure includes the same material as the charge storage structure.
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公开(公告)号：US11557604B2
公开(公告)日：2023-01-17
申请号：US17025120
申请日：2020-09-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seongyeon Woo , Sangjun Hong , Jinsoo Lim , Jisung Cheon
IPC: H01L27/11582 , H01L27/11565 , G11C8/14 , H01L27/11556 , H01L27/11519
Abstract: A semiconductor device includes: a first gate stack including a plurality of first gate electrodes; a second gate stack arranged on the first gate stack and including a plurality of second gate electrodes; and a plurality of channel structures arranged in a plurality of channel holes penetrating the first gate stack and the second gate stack. Each of the channel holes includes a first channel hole portion penetrating the first gate stack and a second channel hole portion penetrating the second gate stack, and a ratio of a second width in the second direction to a first width in the first direction of an upper end of the first channel hole portion is less than a ratio of a fourth width in the second direction to a third width in the first direction of an upper end of the second channel hole portion.
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公开(公告)号：US12010849B2
公开(公告)日：2024-06-11
申请号：US17934959
申请日：2022-09-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jiye Noh , Jinsoo Lim , Daehyun Jang , Jisung Cheon , Sangjun Hong
IPC: H10B43/27 , H01L21/762 , H01L23/48 , H01L23/528 , H10B41/10 , H10B41/35 , H10B41/41 , H10B41/49 , H10B43/10 , H10B43/40
CPC classification number: H10B43/27 , H01L23/481 , H01L23/528 , H10B43/10 , H10B43/40
Abstract: A semiconductor device includes a peripheral circuit structure; a lower stack disposed on the peripheral circuit structure and an upper stack disposed in the lower stack including a plurality of lower insulating layers and a plurality of lower word lines alternately stacked with the lower insulating layers; a plurality of channel structures extending through the lower stack and the upper stack in the cell array area; a pair of separation insulating layers extending vertically through the lower stack and the upper stack and extending in a horizontal direction, the pair of separation insulating layers being spaced apart from each other in a vertical direction; and a word line separation layer disposed at an upper portion of the lower stack and crossing the pair of separation insulating layers when viewed in a plan view, the word line separation layer extending vertically through at least one of the lower word lines.
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公开(公告)号：US11526287B2
公开(公告)日：2022-12-13
申请号：US16828170
申请日：2020-03-24
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyejeong So , Changkyu Seol , Hong Rak Son , Pilsang Yoon , Jinsoo Lim , Jae Hun Jang , Seonghyeong Choi
Abstract: A storage device is provided including a memory controller having a neural processing unit (NPU); a first nonvolatile memory (NVM) connected to the memory controller through a first channel; and a second NVM connected to the memory controller through a second channel. The first NVM stores first weight data for the NPU and the second stores second weight data for the NPU. The memory controller is configured to determine one of the first and second channels that is less frequently accessed upon receiving an inference request from the neural processor, and access a corresponding one of the first weight data and the second weight data using the determined one channel.
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Patent Agency Ranking
6.发明授权公开(公告)号：US09117923B2
公开(公告)日：2015-08-25
申请号：US13830208
申请日：2013-03-14
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sunil Shim , Jaehoon Jang , Hansoo Kim , Sungmin Hwang , Wonseok Cho , Jinsoo Lim
IPC: H01L29/792 , H01L27/115
CPC classification number: H01L29/7926 , H01L27/11556 , H01L27/11582
Abstract: A method of forming a semiconductor memory device includes stacking a plurality of alternating first insulating layers and first sacrificial layers on a substrate to form a first multilayer structure, forming a first hole through the first multilayer structure, forming a first semiconductor pattern in the first hole, stacking a plurality of alternating second insulating layers and second sacrificial layers on the first multilayer structure to form a second multilayer structure, forming a second hole through the second multilayer structure to be aligned with the first hole, forming a second semiconductor pattern in the second hole, forming a trench to expose sidewalls of the first and second insulating layers at a side of the first and second semiconductor patterns, removing at least some portions of the first and second sacrificial layers to form a plurality of recess regions, forming an information storage layer, and forming a conductive pattern.
Abstract translation: 一种形成半导体存储器件的方法包括在衬底上堆叠多个交替的第一绝缘层和第一牺牲层以形成第一多层结构，通过第一多层结构形成第一孔，在第一孔中形成第一半导体图案 在所述第一多层结构上堆叠多个交替的第二绝缘层和第二牺牲层以形成第二多层结构，通过所述第二多层结构形成与所述第一孔对准的第二孔，在所述第二多层结构中形成第二半导体图案 形成沟槽，以在第一和第二半导体图案的一侧露出第一绝缘层和第二绝缘层的侧壁，去除第一和第二牺牲层的至少一部分以形成多个凹陷区域，形成信息存储器 层，形成导电图案。
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公开(公告)号：US12219763B2
公开(公告)日：2025-02-04
申请号：US17744092
申请日：2022-05-13
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jisung Cheon , Byunggon Park , Joowon Park , Sangjun Hong , Jinsoo Lim
IPC: H10B43/27 , H01L21/28 , H01L21/768 , H01L23/522 , H01L23/528 , H01L23/535 , H10B41/27 , H10B41/35 , H10B43/35
Abstract: An integrated circuit device including a substrate having a cell and interconnection region; and a first stacked structure and a second stacked structure on the first stacked structure, each of the first and second stacked structures including insulating layers and word line structures that are alternately stacked one by one on the substrate in the cell region and the interconnection region, wherein, in the interconnection region the first stacked structure includes a first dummy channel hole penetrating through the first stacked structure, the second stacked structure includes a second dummy channel hole communicatively connected to the first dummy channel hole, the second dummy channel hole penetrating through the second stacked structure, respectively, and a first dummy upper width of an uppermost end of the first dummy channel hole is greater than a second dummy upper width of an uppermost end of the second dummy channel hole.
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公开(公告)号：US20250036520A1
公开(公告)日：2025-01-30
申请号：US18420877
申请日：2024-01-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jinsoo Lim , Changkyu Seol , Myoungbo Kwak , Daewook Kim , Dongjin Park , Hyoungbae Ahn , Youngdon Choi , Junghwan Choi
IPC: G06F11/10
Abstract: An electronic device may include a reception circuit configured to generate a plurality of reception data bits based on a voltage level of an analog signal received through a link, and to generate a plurality of bit reliability values indicating probabilities of error occurrence of the plurality of reception data bits based on the voltage level of the analog signal, an alignment circuit configured to group the plurality of reception data bits into a plurality of error correction code (ECC) symbols, and to generate a plurality of symbol reliability values indicating probabilities of error occurrence of the plurality of ECC symbols based on the plurality of bit reliability values, and a decoding circuit configured to correct errors of the plurality of ECC symbols based on the plurality of symbol reliability values.
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公开(公告)号：US12052032B2
公开(公告)日：2024-07-30
申请号：US18055867
申请日：2022-11-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jinsoo Lim , Changkyu Seol , Myoungbo Kwak , Pilsang Yoon
CPC classification number: H03M13/09 , H03M13/1125 , H03M13/45
Abstract: Disclosed is an electronic device, which includes an ECC decoder that performs ECC decoding on a flit including a plurality of PAM-4 symbols for each of a plurality of ECC groups, a CRC decoder that performs CRC decoding on the ECC decoded flit to obtain data, and an erasure decoding unit that calculates an LLR for each of the PAM-4 symbols when the CRC decoding fails, extracts an error symbol candidate from among the plurality of PAM-4 symbols for each of the plurality of ECC groups based on the LLR, and performs the ECC decoding again after erasing the error symbol candidate.
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公开(公告)号：US20240178863A1
公开(公告)日：2024-05-30
申请号：US18511740
申请日：2023-11-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jinsoo Lim , Changkyu Seol , Myoungbo Kwak , Daewook Kim , Dongjin Park , Youngdon Choi
CPC classification number: H03M13/1595 , H03M13/2778 , H03M13/2927
Abstract: A device includes a receiver configured to receive a plurality of Error Correction Code (ECC) codewords transmitted from an external device through a channel including one or more lanes; an ECC decoder configured to generate a plurality of post ECC codewords by performing error correction with respect to the plurality of ECC codewords and generating a first cyclic redundancy check (CRC) codeword based on the plurality of post ECC codewords; a CRC checker configured to determine whether an error exists in the first CRC codeword; and a post ECC decoder configured to, when it is determined that the error exists in the first CRC codeword, generate a second CRC codeword by estimating a remaining error position based on error correction result information received from the ECC decoder and performing remaining error correction with respect to the plurality of post ECC codewords based on the remaining error position.
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