公开(公告)号：US11417395B2

公开(公告)日：2022-08-16

申请号：US17036378

申请日：2020-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoon Sung Shin ,  Kwang Jin Lee

IPC: G11C13/00 ,  G06F3/06

Abstract: A phase change memory system comprises a phase change memory device which includes a plurality of memory units including a plurality of memory cells in units of at least one or more codewords and a phase change memory controller which performs a chip refresh operation for refreshing the entire phase change memory device, wherein the phase change memory device includes a setting circuitry which determines one of the plurality of memory units in a desired manner, a refresh controller which refreshes the decided memory unit, a sensing circuitry which senses data of at least one or more codewords included in the refreshed memory unit, and a request circuitry which requests a host for the chip refresh operation on the basis of a result of the sensing operation.

公开(公告)号：US11056187B2

公开(公告)日：2021-07-06

申请号：US16034921

申请日：2018-07-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae Hui Na ,  Mu Hui Park ,  Kwang Jin Lee ,  Yong Jun Lee

IPC: G11C13/00 ,  H01L45/00

Abstract: A memory device includes a memory cell array including a plurality of memory cells, each of the plurality of memory cells having a switch element, and a data storage element connected to the switch element and containing a phase-change material; and a memory controller for obtaining first read voltages from the plurality of memory cells, inputting a first write current to the plurality of memory cells, and then, obtaining second read voltages from the plurality of memory cells, wherein the memory controller compares the first read voltage of a first memory cell of the plurality of memory cells to the second read voltage of the first memory cell to determine a state of the first memory cell.

公开(公告)号：US11948631B2

公开(公告)日：2024-04-02

申请号：US17314161

申请日：2021-05-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae Hui Na ,  Mu Hui Park ,  Kwang Jin Lee ,  Yong Jun Lee

IPC: G11C11/00 ,  G11C13/00 ,  H10N70/20

CPC classification number: G11C13/0004 ,  G11C13/004 ,  H10N70/231 ,  G11C2013/0057 ,  G11C2213/72 ,  G11C2213/76

Abstract: A memory device includes a memory cell array including a plurality of memory cells, each of the plurality of memory cells having a switch element, and a data storage element connected to the switch element and containing a phis change material; and a memory controller for obtaining first read voltages from the plurality of memory cells, inputting a first write current to the plurality of memory cells, and then, obtaining second read voltages from the plurality of memory cells, wherein the memory controller compares the first read voltage of a first memory cell of the plurality of memory cells to the second read voltage of the first memory cell to determine a state of the first memory cell.