公开(公告)号：US20220310594A1

公开(公告)日：2022-09-29

申请号：US17569363

申请日：2022-01-05

申请人： Samsung Electronics Co., Ltd.

发明人： Youncheol Jeong ,  Jaeung Koo ,  Kwansung Kim ,  Seungyoon Kim ,  Boun Yoon ,  Jooho Jung ,  Sukbae Joo

IPC分类号： H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

摘要： A semiconductor device includes an active region extending in a first direction on a substrate, a plurality of channel layers vertically spaced apart from each other on the active region, a gate structure vertically overlapping the active region and the plurality of channel layers on the substrate, extending in a second direction, and including a gate electrode surrounding the plurality of channel layers and a gate capping layer disposed on an upper surface of the gate electrode, a first source/drain region disposed on a side of the gate structure on the active region and in contact with the plurality of channel layers, an isolation structure intersecting the active region on the substrate, extending in the second direction, and disposed between the first source/drain region and a second source/drain region adjacent to each other, and contact structures in contact with the source/drain regions.

公开(公告)号：US11094586B2

公开(公告)日：2021-08-17

申请号：US16539064

申请日：2019-08-13

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Seung Hoon Choi ,  Jaeung Koo ,  Kwansung Kim ,  Bo Yun Kim ,  Wandon Kim ,  Boun Yoon ,  Jeonghyuk Yim ,  Yeryung Jeon

IPC分类号： H01L21/768 ,  H01L27/105 ,  H01L23/528 ,  H01L23/532 ,  H01L21/3105

摘要： A semiconductor device and a method of fabricating a semiconductor device, the semiconductor device including a semiconductor substrate including a first region and a second region; an interlayer insulating layer on the semiconductor substrate, the interlayer insulating layer including a first opening on the first region and having a first width; and a second opening on the second region and having a second width, the second width being greater than the first width; at least one first metal pattern filling the first opening; a second metal pattern in the second opening; and a filling pattern on the second metal pattern in the second opening, wherein the at least one first metal pattern and the second metal pattern each include a same first metal material, and the filling pattern is formed of a non-metal material.

公开(公告)号：US09997412B1

公开(公告)日：2018-06-12

申请号：US15646300

申请日：2017-07-11

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Ki Ho Bae ,  Jaeseok Kim ,  Hoyoung Kim ,  Boun Yoon ,  KyungTae Lee ,  Kwansung Kim ,  Eunji Park

IPC分类号： H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L21/321 ,  H01L29/66

CPC分类号： H01L21/823475 ,  H01L21/823418 ,  H01L21/823437

摘要： A method of manufacturing a semiconductor device includes forming on a substrate gate electrodes extending in a first direction and spaced apart from each other in a second direction, forming capping patterns on the gate electrodes, forming interlayer dielectric layer filling spaces between adjacent gate electrodes, forming a hardmask on the interlayer dielectric layer with an opening selectively exposing second to fourth capping patterns, using the hardmask as an etch mask to form holes in the interlayer dielectric layer between the second and third gate electrodes and between the third and fourth gate electrodes, forming a barrier layer and a conductive layer in the holes, performing a first planarization to expose the hardmask, performing a second planarization to expose a portion of the barrier layer covering the second to fourth capping patterns, and performing a third planarization to completely expose the first to fourth capping patterns.