公开(公告)号：US10446495B2

公开(公告)日：2019-10-15

申请号：US15909390

申请日：2018-03-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoonhee Kang ,  Jiyoung Kim ,  Taejin Yim ,  Jongmin Baek ,  Sanghoon Ahn ,  Hyeoksang Oh ,  Kyu-Hee Han

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/02

Abstract: Embodiments of the present inventive concepts provide methods of forming an ultra-low-k dielectric layer and the ultra-low-k dielectric layer formed thereby. The method may include forming a first layer by supplying a precursor including silicon, oxygen, carbon, and hydrogen, performing a first ultraviolet process on the first layer to convert the first layer into a second layer, and performing a second ultraviolet process on the second layer under a process condition different from that of the first ultraviolet process.

公开(公告)号：US20140312456A1

公开(公告)日：2014-10-23

申请号：US14256232

申请日：2014-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoung-Hee Kim ,  Ho-Ki Lee ,  Gilheyun Choi ,  Kyu-Hee Han ,  Jongwon Hong

IPC: H01L29/06 ,  H01L23/535

CPC classification number: H01L29/0649 ,  H01L21/764 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device can include wiring lines on a substrate and an interlayer insulating structure, between ones of the wiring lines. The wiring lines can include a pore-containing layer that includes a plurality of pores extending away from a surface of the substrate, wherein ones of the pores have respective volumes that increase with a distance from the substrate until reaching an air gap layer above the pore-containing layer and beneath uppermost surfaces of the wiring lines.

Abstract translation: 半导体器件可以包括衬底上的布线和层间绝缘结构，在布线之间。 布线可以包括含孔层，其包括远离衬底表面延伸的多个孔，其中孔中的一些孔具有随着与衬底的距离而增加的体积，直到达到孔的上方的气隙层 并且在布线的最上表面之下。

公开(公告)号：US11881430B2

公开(公告)日：2024-01-23

申请号：US17826366

申请日：2022-05-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Jin Kang ,  Jong Min Baek ,  Woo Kyung You ,  Kyu-Hee Han ,  Han Seong Kim ,  Jang Ho Lee ,  Sang Shin Jang

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76808 ,  H01L23/481 ,  H01L21/76832

Abstract: A semiconductor device including a first interlayer insulating film; a conductive pattern in the first interlayer insulating film; a resistance pattern on the conductive pattern; an upper etching stopper film spaced apart from the resistance pattern, extending in parallel with a top surface of the resistance pattern, and including a first metal; a lower etching stopper film on the conductive pattern, extending in parallel with a top surface of the first interlayer insulating film, and including a second metal; and a second interlayer insulating film on the upper etching stopper film and the lower etching stopper film, wherein a distance from a top surface of the second interlayer insulating film to a top surface of the upper etching stopper film is smaller than a distance from the top surface of the second interlayer insulating film to a top surface of the lower etching stopper film.

公开(公告)号：US09312171B2

公开(公告)日：2016-04-12

申请号：US14490964

申请日：2014-09-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyu-Hee Han ,  Pil-Kyu Kang ,  Taejin Yim ,  Naein Lee

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76879 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present inventive concepts provide semiconductor devices and methods for fabricating the same. The method includes forming an inter-metal dielectric layer including a plurality of dielectric layers on a substrate, forming a via-hole vertically penetrating the inter-metal dielectric layer and the substrate, providing carbon to at least one surface, such as a surface including carbon in the plurality of dielectric layers exposed by the via-hole, forming a via-dielectric layer covering an inner surface of the via-hole, and forming a through-electrode surrounded by the via-dielectric layer in the via-hole.

Abstract translation: 本发明构思提供半导体器件及其制造方法。 该方法包括在基板上形成包括多个电介质层的金属间介电层，形成垂直贯穿金属间介电层和基板的通孔，向至少一个表面提供碳，例如包括 通过通孔露出的多个电介质层中的碳，形成覆盖通路孔的内表面的通孔电介质层，以及形成由通路孔中的通孔电介质层包围的贯通电极。

公开(公告)号：US08569862B2

公开(公告)日：2013-10-29

申请号：US13792996

申请日：2013-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Hoon Ahn ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Sang-Don Nam ,  Kyu-Hee Han

IPC: H01L33/00

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A fuse base insulating region, for example, an insulating interlayer or a compensation region disposed in an insulating interlayer, is formed on a substrate. An etch stop layer is formed on the fuse base insulating region and forming an insulating interlayer having a lower dielectric constant than the first fuse base insulating region on the etch stop layer. A trench extending through the insulating interlayer and the etch stop layer and at least partially into the fuse base insulating region is formed. A fuse is formed in the trench. The fuse base insulating region may have a greater mechanical strength and/or density than the second insulating interlayer.

Abstract translation: 在衬底上形成熔丝基底绝缘区域，例如绝缘中间层或设置在绝缘中间层中的补偿区域。 在熔丝基底绝缘区上形成蚀刻停止层，形成绝缘中间层，该绝缘中间层的介电常数比蚀刻停止层上的第一熔丝基底绝缘区低。 形成了延伸穿过绝缘中间层和蚀刻停止层并且至少部分地进入熔丝基底绝缘区域的沟槽。 在沟槽中形成熔丝。 保险丝座绝缘区域可具有比第二绝缘中间层更大的机械强度和/或密度。

公开(公告)号：US20130193552A1

公开(公告)日：2013-08-01

申请号：US13792996

申请日：2013-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Hoon Ahn ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Sang-Don Nam ,  Kyu-Hee Han

IPC: H01L23/525

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A fuse base insulating region, for example, an insulating interlayer or a compensation region disposed in an insulating interlayer, is formed on a substrate. An etch stop layer is formed on the fuse base insulating region and forming an insulating interlayer having a lower dielectric constant than the first fuse base insulating region on the etch stop layer. A trench extending through the insulating interlayer and the etch stop layer and at least partially into the fuse base insulating region is formed. A fuse is formed in the trench. The fuse base insulating region may have a greater mechanical strength and/or density than the second insulating interlayer.

Abstract translation: 在衬底上形成熔丝基底绝缘区域，例如绝缘中间层或设置在绝缘中间层中的补偿区域。 在熔丝基底绝缘区上形成蚀刻停止层，形成绝缘中间层，该绝缘中间层的介电常数比蚀刻停止层上的第一熔丝基底绝缘区低。 形成了延伸穿过绝缘中间层和蚀刻停止层并且至少部分地进入熔丝基底绝缘区域的沟槽。 在沟槽中形成熔丝。 保险丝座绝缘区域可具有比第二绝缘中间层更大的机械强度和/或密度。

公开(公告)号：US11837618B1

公开(公告)日：2023-12-05

申请号：US16999926

申请日：2020-08-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaesung Hur ,  Taeksoo Jeon ,  Jongmin Baek ,  Sanghoon Ahn ,  Jangho Lee ,  Kyu-Hee Han

IPC: H01L27/146

CPC classification number: H01L27/14627 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14685 ,  H01L27/1463 ,  H01L27/14645

Abstract: An image sensor includes a semiconductor substrate having a plurality of pixel regions arranged in a first direction and a second direction that are parallel to an upper surface of the semiconductor substrate. The first direction is perpendicular to the second direction. A grid structure extends in the first direction and the second direction on the semiconductor substrate to define openings corresponding to a plurality of sub-pixel regions of the plurality of the pixel regions, respectively. Color filters are disposed in the openings of the grid structure, respectively. A protective layer covers sidewalls of the grid structure and bottom surfaces of the color filters. The protective layer includes silicon oxide including carbon (C) or nitrogen (N).

公开(公告)号：US11823952B2

公开(公告)日：2023-11-21

申请号：US18079998

申请日：2022-12-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woojin Lee ,  Hoon Seok Seo ,  Sanghoon Ahn ,  Kyu-Hee Han

IPC: H01L23/528 ,  H01L21/768

CPC classification number: H01L21/76897 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/5283

Abstract: A semiconductor device includes a substrate including an active pattern, a first interlayer dielectric layer on the substrate, the first interlayer dielectric layer including a recess on an upper portion thereof, and a lower connection line in the first interlayer dielectric layer, the lower connection line being electrically connected to the active pattern, and the lower connection line including a conductive pattern, the recess of the first interlayer dielectric layer selectively exposing a top surface of the conductive pattern, and a barrier pattern between the conductive pattern and the first interlayer dielectric layer, the first interlayer dielectric layer covering a top surface of the barrier pattern.

公开(公告)号：US11139244B2

公开(公告)日：2021-10-05

申请号：US16793366

申请日：2020-02-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jangho Lee ,  Jongmin Baek ,  Wookyung You ,  Kyu-Hee Han ,  Suhyun Bark

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522

Abstract: Disclosed is a semiconductor device comprising a substrate, a first dielectric layer on the substrate, a first lower conductive line in the first dielectric layer, an etch stop layer on the first dielectric layer, a via-structure that penetrates the etch stop layer and connects to the first lower conductive line, a second dielectric layer on the etch stop layer, and an upper conductive line that penetrates the second dielectric layer and connects to the via-structure. The first dielectric layer includes a dielectric pattern at a level higher than a top surface of the first lower conductive line. The upper conductive line is in contact with a top surface of the etch stop layer. The etch stop layer has at an upper portion a rounded surface in contact with the via-structure.

公开(公告)号：US10777449B2

公开(公告)日：2020-09-15

申请号：US16242483

申请日：2019-01-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Shin Jang ,  Woo-Kyung You ,  Kyu-Hee Han ,  Jong-Min Baek ,  Viet Ha Nguyen ,  Byung-Hee Kim

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor device includes a first insulating interlayer on a first region of a substrate and a second insulating interlayer on a second region of the substrate, a plurality of first wiring structures on the first insulating interlayer, the first wiring structures being spaced apart from each other, a plurality of second wiring structures filling a plurality of trenches on the second insulating interlayer, respectively, an insulation capping structure selectively on a surface of the first insulating interlayer between the first wiring structures and on a sidewall and an upper surface of each of the first wiring structures, the insulation capping structure including an insulating material, a third insulating interlayer on the first and second wiring structures, and an air gap among the first wiring structures under the third insulating interlayer.