公开(公告)号：US20240363665A1

公开(公告)日：2024-10-31

申请号：US18384025

申请日：2023-10-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minho JANG ,  Doowon KWON ,  Doyeon KIM ,  GwideokRyan LEE ,  Kyungtae LIM

IPC: H01L27/146 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L27/14634 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/08 ,  H01L27/14636 ,  H01L2224/08145

Abstract: A semiconductor device includes a first substrate having a first semiconductor layer with a first electronic element, a first insulation layer on the first semiconductor layer, a first conductive pad in the first insulation layer and exposed through a first side of the first substrate, and a first wire in the first insulation layer connected to the first semiconductor layer, and a second substrate attached to the first side of the first substrate and having a second semiconductor layer with a second electronic element, a second insulation layer on the second semiconductor layer, a second wire in the second insulation layer, a through via penetrating the second semiconductor layer and connected to the second wire, and a second conductive pad connecting the through via and the first conductive pad of the first substrate, at least a part of the second conductive pad being in the second semiconductor layer.

公开(公告)号：US20240178259A1

公开(公告)日：2024-05-30

申请号：US18354040

申请日：2023-07-18

Applicant: Samsung Electronics Co,, Ltd.

Inventor： Doowon KWON ,  Minho JANG ,  Kyungtae LIM ,  Doyeon KIM ,  Haejung LEE

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/14607 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1463 ,  H01L27/14632 ,  H01L27/14685 ,  H01L27/14687

Abstract: The inventive concepts provide a three-layered stacked image sensor in which misalignment between a through electrode and a pad is reduced and coupling noise between adjacent pads is reduced, and methods of manufacturing the same. The three-layered stacked image sensor includes an upper chip including pixels arranged in a two-dimensional array structure and a first wiring layer, each of pixels including a photodiode, a transfer gate, and a floating diffusion region, an intermediate chip including a source follower gate, a select gate, and a reset gate corresponding to each of pixels, a first silicon layer, and a second wiring layer, and a lower chip including an image sensor processor, a third wiring layer, and a second silicon layer, a cross-section of an upper portion of a through electrode extending from the second wiring layer through the first silicon layer having an inverted trapezoidal structure.