公开(公告)号：US20170243918A1

公开(公告)日：2017-08-24

申请号：US15257609

申请日：2016-09-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Masayuki TERAI ,  Gwan-hyeob KOH ,  Dae-hwan KANG

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2427 ,  G11C11/1659 ,  G11C13/0002 ,  G11C13/003 ,  G11C2213/17 ,  G11C2213/71 ,  G11C2213/76 ,  G11C2213/79 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/11582 ,  H01L27/2454 ,  H01L27/2481 ,  H01L27/249 ,  H01L43/08 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675

Abstract: A memory device may include a substrate, a first conductive line on the substrate and extending in a first direction, a second conductive line over the first conductive line and extending in a second direction crossing the first direction, a third conductive line over the second conductive line and extending in the first direction, a first memory cell at an intersection of the first conductive line and the second conductive line and including a first selection element layer and a first variable resistance layer, and a second memory cell at an intersection of the second conductive line and the third conductive line and including a second selection element layer and a second variable resistance layer. A first height of the first selection element layer in a third direction perpendicular to the first and second directions is different than a second height of the second selection element layer in the third direction.

公开(公告)号：US20170294483A1

公开(公告)日：2017-10-12

申请号：US15632969

申请日：2017-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Masayuki TERAI ,  Gwan-hyeob KOH ,  Dae-hwan KANG

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2427 ,  G11C11/1659 ,  G11C13/0002 ,  G11C13/003 ,  G11C2213/17 ,  G11C2213/71 ,  G11C2213/76 ,  G11C2213/79 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/11582 ,  H01L27/2454 ,  H01L27/2481 ,  H01L27/249 ,  H01L43/08 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675

Abstract: A memory device may include a substrate, a first conductive line on the substrate and extending in a first direction, a second conductive line over the first conductive line and extending in a second direction crossing the first direction, a third conductive line over the second conductive line and extending in the first direction, a first memory cell at an intersection of the first conductive line and the second conductive line and including a first selection element layer and a first variable resistance layer, and a second memory cell at an intersection of the second conductive line and the third conductive line and including a second selection element layer and a second variable resistance layer. A first height of the first selection element layer in a third direction perpendicular to the first and second directions is different than a second height of the second selection element layer in the third direction.

公开(公告)号：US20170117328A1

公开(公告)日：2017-04-27

申请号：US15334750

申请日：2016-10-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Masayuki TERAI

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2481 ,  H01L27/2427 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1266 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1675

Abstract: A semiconductor device includes: a first memory cell, a bit line and a second memory cell. The first memory cell has a first stack structure including a first memory layer between a first heater electrode and a first ovonic threshold switching device. The bit line is on the first memory cell. The second memory cell is on the bit line, and has a second stack structure including a second memory layer between a second ovonic threshold switching device and a second heater electrode. The first and second stack structures are symmetrical with respect to the bit line.

公开(公告)号：US20250063727A1

公开(公告)日：2025-02-20

申请号：US18680554

申请日：2024-05-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minhee CHO ,  Hyeran LEE ,  Masayuki TERAI

IPC: H10B12/00 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device includes an upper conductive line extending in a first horizontal direction over a substrate, a channel layer facing the upper conductive line in a second horizontal direction that is perpendicular to the first horizontal direction, a gate dielectric film between the channel layer and the upper conductive line, a conductive contact pattern including a lower surface, which is in contact with an upper surface of the channel layer, and sidewalls including a first sidewall, which faces the upper conductive line in the second horizontal direction, and an insulating spacer including a first portion between the upper conductive line and the conductive contact pattern in the second horizontal direction.

公开(公告)号：US20190252464A1

公开(公告)日：2019-08-15

申请号：US16394494

申请日：2019-04-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Masayuki TERAI

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/249 ,  H01L27/2427 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/065 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/141 ,  H01L45/144 ,  H01L45/1683

Abstract: A semiconductor device including a data storage pattern is provided. The semiconductor device includes a first conductive line disposed on a substrate and extending in a first direction, a second conductive line disposed on the first conductive line and extending in a second direction, and a first data storage structure and a first selector structure disposed between the first conductive line and the second conductive line and connected in series. The first data storage structure includes a first lower data storage electrode, a first data storage pattern, and a first upper data storage electrode. The first lower data storage electrode includes a first portion facing the first upper data storage electrode and vertically aligned with the first upper data storage electrode. The first data storage pattern includes a first side surface and a second side surface facing each other. The first upper data storage electrode and the first portion of the first lower data storage electrode are disposed to be closer to the first side surface of the first data storage pattern than to the second side surface of the first data storage pattern.

公开(公告)号：US20180166502A1

公开(公告)日：2018-06-14

申请号：US15630169

申请日：2017-06-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Masayuki TERAI

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2481 ,  H01L27/24 ,  H01L27/2427 ,  H01L45/00 ,  H01L45/06 ,  H01L45/1253 ,  H01L45/141 ,  H01L45/165

Abstract: Some example embodiments relate to a semiconductor device including a line pattern, the line pattern having threshold switching devices. The semiconductor device includes a line pattern disposed on a semiconductor substrate. The line pattern includes threshold switching devices and switch separation regions. Data storage patterns may overlap the threshold switching devices. Intermediate electrodes may be disposed between the data storage patterns and the threshold switching devices. The line pattern includes an impurity element, and the concentration of the impurity element in the switch separation regions is higher than the concentration of the impurity element in the threshold switching devices.