公开(公告)号：US20230197806A1

公开(公告)日：2023-06-22

申请号：US18113116

申请日：2023-02-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Namgyu CHO ,  Minwoo SONG ,  Ohseong KWON ,  Wandon KIM ,  Hyeokjun SON ,  Jinkyu JANG

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/775 ,  H01L29/66

CPC classification number: H01L29/41791 ,  H01L29/7855 ,  H01L29/4236 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/0673 ,  H01L29/78696 ,  H01L29/775 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7854 ,  H01L29/66439 ,  H01L29/4966

Abstract: A semiconductor device includes: an active fin disposed on a substrate; a gate structure overlapping the active fin; source/drain regions disposed on both sides of the gate structure and on the active fin; and contact structures respectively connected to the source/drain regions, wherein the gate structure includes: a pair of gate spacers spaced apart from each other to provide a trench; a first gate electrode disposed in the trench and extending along an upper surface and a lateral surface of the active fin; a second gate electrode disposed on the first gate electrode in the trench, wherein the first gate electrode is not disposed between the second gate electrode and the pair of gate spacers; and a gate insulating film disposed between the pair of gate spacers and interposed between the first gate electrode and the active fin.

公开(公告)号：US20200176317A1

公开(公告)日：2020-06-04

申请号：US16785236

申请日：2020-02-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Namgyu CHO ,  Kughwan Kim ,  Geunwoo Kim ,  Jungmin Park ,  Minwoo Song

IPC: H01L21/8234 ,  H01L29/40 ,  H01L21/3213 ,  H01L29/66

Abstract: A method of fabricating a semiconductor device may include forming a first conductive layer on first to third regions of a substrate, forming a barrier layer on the first conductive layer, the barrier layer including a first barrier layer, a second barrier layer, and a sacrificial layer which are sequentially formed, sequentially forming a second conductive layer and a third conductive layer on the barrier layer, performing a first etching process to remove the third conductive layer from the second region and the third region, the third conductive layer remaining on the first region after the first etching process, and performing a second etching process to remove the second conductive layer and the sacrificial layer from the third region, the second conductive layer and the sacrificial layer remaining on the first region and on the second region after the second etching process.