公开(公告)号：US20210225429A1

公开(公告)日：2021-07-22

申请号：US16925049

申请日：2020-07-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seongil O ,  Namsung KIM ,  Sukhan LEE

IPC: G11C11/4096 ,  G11C11/4091 ,  G11C11/408 ,  G11C7/10 ,  G06F9/30 ,  G06F9/38

Abstract: A high bandwidth memory and a system having the same are disclosed. The high bandwidth memory includes a buffer die and a plurality of memory dies, each of which includes at least one first processing element bank group and at least one second processing element bank group. The at least one first processing element bank group includes one or more first banks connected to one or more first bank input/output line groups, and a first processing element controller connected to the one or more first bank input/output line groups and a first global input/output line group, and is configured to perform a first processing operation on first data output from one of the one or more first bank input/output line groups and second data transmitted through the first global input/output line group based on a first instruction that is generated based on a first processing command.

公开(公告)号：US20230275183A1

公开(公告)日：2023-08-31

申请号：US18114785

申请日：2023-02-27

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： JAIWON JEAN ,  Namsung KIM ,  Yuri SOHN ,  Daemyung CHUN

IPC: H01L33/20 ,  H01L25/075

CPC classification number: H01L33/20 ,  H01L25/0756

Abstract: A light emitting device is provided. The light emitting device includes: a first semiconductor layer; a dislocation blocking layer on an upper surface of the first semiconductor layer and having a plurality of holes formed therein; a second semiconductor layer on the dislocation blocking layer; a third semiconductor layer on the second semiconductor layer; an active layer on the third semiconductor layer; and a fourth semiconductor layer on the active layer. A plurality of voids, which respectively overlap the plurality of holes along a vertical direction perpendicular to the upper surface of the first semiconductor layer, are provided between the first semiconductor layer and the second semiconductor layer.

公开(公告)号：US20230030530A1

公开(公告)日：2023-02-02

申请号：US17964957

申请日：2022-10-13

Applicant: SAMSUNG ELECTRONICS Co., LTD.

Inventor： Jaiwon JEAN ,  Joongseo KANG ,  Namsung KIM ,  Daemyung CHUN

IPC: H01L33/12 ,  H01L33/22 ,  H01L27/15 ,  H01L33/32

Abstract: A semiconductor light-emitting device includes a buffer structure, a first-type semiconductor layer on the buffer structure, an active layer on the first-type semiconductor layer, and a second-type semiconductor layer on the active layer. The buffer structure includes a nucleation layer, a first dislocation-removing structure on the nucleation layer, and a buffer layer on the first dislocation-removing structure. The first dislocation-removing structure includes a first material layer on the nucleation layer and a second material layer on the first material layer. The second material layer has a lattice constant different from a lattice constant of the first material layer. A roughness of a top surface of the first material layer is higher than a roughness of a top surface of the nucleation layer and higher than a roughness of a top surface of the second material layer.

公开(公告)号：US20220085257A1

公开(公告)日：2022-03-17

申请号：US17323042

申请日：2021-05-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiwon PARK ,  Namsung KIM ,  Youngsub SHIN ,  Jonghyun LEE ,  Daemyung CHUN ,  Byungchul CHOI

IPC: H01L33/50 ,  H01L27/15 ,  H01L33/00 ,  H01L33/38 ,  H01L33/46

Abstract: A semiconductor light emitting device including a semiconductor laminate having first and second surfaces, the semiconductor laminate including first and second conductivity-type semiconductor layers, and an active layer between the semiconductor layers; a partition structure on the first surface, the partition structure having a window defining a light emitting region of the first surface of the semiconductor laminate; a wavelength converter in the window, the wavelength converter being configured to convert a wavelength of light emitted from the active layer; and a first electrode and a second electrode on the second surface of the semiconductor laminate and respectively connected to the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer, wherein the semiconductor laminate includes a plurality of first patterns arranged in the light emitting region of the first surface, and a plurality of second patterns arranged in a covered region of the first surface contacting the partition structure.

公开(公告)号：US20220406369A1

公开(公告)日：2022-12-22

申请号：US17899141

申请日：2022-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngcheon KWON ,  Jaeyoun YOUN ,  Namsung KIM ,  Kyomin SOHN ,  Seongil O ,  Sukhan LEE

IPC: G11C11/406 ,  G11C7/10 ,  G11C11/4076 ,  G11C11/408

Abstract: A memory device including: a plurality of pins for receiving control signals from an external device; a first bank having first memory cells, wherein the first bank is activated in a first operation mode and a second operation mode; a second bank having second memory cells, wherein the second bank is deactivated in the first operation mode and activated in the second operation mode; a processing unit configured to perform an operation on first data, output from the first memory cells, and second data, output from the second memory cells, in the second operation mode; and a processing-in-memory (PIM) mode controller configured to select mode information, indicating one of the first operation mode and the second operation mode, in response to the control signals and to control at least one memory parameter, at least one mode register set (MRS) value, or a refresh mode according to the mode information.

公开(公告)号：US20220068366A1

公开(公告)日：2022-03-03

申请号：US17239854

申请日：2021-04-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngcheon KWON ,  Jaeyoun YOUN ,  Namsung KIM ,  Kyomin SOHN ,  Seongil O ,  Sukhan LEE

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/408 ,  G11C7/10

Abstract: A memory device including: a plurality of pins for receiving control signals from an external device; a first bank having first memory cells, wherein the first bank is activated in a first operation mode and a second operation mode; a second bank having second memory cells, wherein the second bank is deactivated in the first operation mode and activated in the second operation mode; a processing unit configured to perform an operation on first data, output from the first memory cells, and second data, output from the second memory cells, in the second operation mode; and a processing-in-memory (PIM) mode controller configured to select mode information, indicating one of the first operation mode and the second operation mode, in response to the control signals and to control at least one memory parameter, at least one mode register set (MRS) value, or a refresh mode according to the mode information.

公开(公告)号：US20210311821A1

公开(公告)日：2021-10-07

申请号：US17088900

申请日：2020-11-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yesin Ryu ,  Namsung KIM ,  Sanguhn CHA ,  Jaeyoun Youn ,  Kijun Lee

IPC: G06F11/10 ,  H01L25/065

Abstract: A semiconductor memory device including: a buffer die; memory dies stacked on the buffer die; and TSVs, at least one of the memory dies includes: a memory cell array; an error correction code (ECC) engine; an error information register; and a control logic circuit configured to control the ECC engine to perform a read-modify-write operation, wherein the control logic circuit is configured to: record, in the error information register, a first address associated with a first codeword based on the an generation signal and a first syndrome obtained by an ECC decoding; and determine an error attribute of the first codeword based on a change of the first syndrome, recorded in the error information register, based on a plurality of read-modify-write operations.

公开(公告)号：US20210287735A1

公开(公告)日：2021-09-16

申请号：US17333366

申请日：2021-05-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seongil O ,  Namsung KIM ,  Sukhan LEE

IPC: G11C11/4096 ,  G11C11/408 ,  G06F9/30 ,  G11C7/10 ,  G06F9/38 ,  G11C11/4091

Abstract: A high bandwidth memory and a system having the same are disclosed. The high bandwidth memory includes a buffer die and a plurality of memory dies, each of which includes at least one first processing element bank group and at least one second processing element bank group. The at least one first processing element bank group includes one or more first banks connected to one or more first bank input/output line groups, and a first processing element controller connected to the one or more first bank input/output line groups and a first global input/output line group, and is configured to perform a first processing operation on first data output from one of the one or more first bank input/output line groups and second data transmitted through the first global input/output line group based on a first instruction that is generated based on a first processing command.