公开(公告)号：US20210200586A1

公开(公告)日：2021-07-01

申请号：US17003455

申请日：2020-08-26

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： KYUNGBO YANG ,  DAEHYUN KIM ,  DONGIK JEON

IPC分类号： G06F9/48 ,  G06F3/06

摘要： In a method of scheduling jobs in a storage device, a first job is performed. While the first job is being performed, a first timestamp for the first job is pre-updated based on a pre-defined operation time table that represents a relationship between operations of the storage device and operation times. While the first job is being performed, scheduling requests are received that are associated with a second job to be performed after the first job. While the first job is being performed, a scheduling operation for selecting the second job is pre-performed based on the scheduling requests and the timestamps.

公开(公告)号：US20210055888A1

公开(公告)日：2021-02-25

申请号：US17092860

申请日：2020-11-09

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： CHULSEUNG LEE ,  SEONGHOON WOO ,  KYUWOOK HAN ,  DAEHYUN KIM

IPC分类号： G06F3/06 ,  G06F13/28

摘要： A storage device includes a first memory device, a second memory device, and a controller. The first memory device and the second memory device share the same channel to communicate with the controller. Communication between the first memory device and the controller and communication between the second memory device and the controller are mutually exclusive. When the controller receives a read request directed to the second memory device while the controller processes a direct memory access (DMA) operation directed to the first memory device, the controller suspends the DMA operation and transmits a read command associated with the read request to the second memory device.

公开(公告)号：US20240248850A1

公开(公告)日：2024-07-25

申请号：US18416558

申请日：2024-01-18

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： DAEHYUN KIM ,  SEONGMUK KANG ,  JIHO KIM ,  KYOMIN SOHN ,  YEONGGEOL SONG ,  KIJUN LEE ,  MYUNGKYU LEE ,  SUKHAN LEE

IPC分类号： G06F12/0891 ,  G06F12/126

CPC分类号： G06F12/0891 ,  G06F12/126

摘要： A memory system includes a system controller and a memory device. The system controller includes a memory controller configured to transmit a received address to a decoding module, and output, to the host device, decoded data. The decoding module includes a cache device and a decoder. The decoding module is configured to receive the data corresponding to the address from the memory device. The decoding module is configured transmit the data stored in the cache device to the memory controller in response to determining that the data corresponding to the address is stored in the cache device. The decoding module is configured to decode the data corresponding to the address to generate decoded data and store the decoded result in the cache device in response to determining that the data corresponding to the address is not stored in the cache device.

公开(公告)号：US20190079698A1

公开(公告)日：2019-03-14

申请号：US15960644

申请日：2018-04-24

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： CHULSEUNG LEE ,  SEONGHOON WOO ,  KYUWOOK HAN ,  DAEHYUN KIM

IPC分类号： G06F3/06 ,  G06F13/28

摘要： A storage device includes a first memory device, a second memory device, and a controller. The first memory device and the second memory device share the same channel to communicate with the controller. Communication between the first memory device and the controller and communication between the second memory device and the controller are mutually exclusive. When the controller receives a read request directed to the second memory device while the controller processes a direct memory access (DMA) operation directed to the first memory device, the controller suspends the DMA operation and transmits a read command associated with the read request to the second memory device.

公开(公告)号：US20220384410A1

公开(公告)日：2022-12-01

申请号：US17883682

申请日：2022-08-09

申请人： Samsung Electronics Co., Ltd.

发明人： HYUNMOG PARK ,  DAEHYUN KIM ,  JINMIN KIM ,  HEI SEUNG KIM ,  HYUNSIK PARK ,  SANGKIL LEE

IPC分类号： H01L25/18 ,  G11C14/00 ,  G11C16/04 ,  H01L25/00 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/48

摘要： Disclosed are fusion memory devices and methods of fabricating the same. The fusion memory device comprises a first memory device including a first substrate having active and inactive surfaces opposite to each other and a first memory cell circuit on the active surface of the first substrate, a non-memory device including a second substrate having active and inactive surfaces opposite to each other and a non-memory circuit on the active surface of the second substrate, the non-memory device being provided on the first memory device, and a second memory device on the inactive surface of the second substrate and including a second memory cell circuit different from the first memory cell circuit. The non-memory device lies between the first and second memory cell circuits and controls an electrical operation of each of the first and second memory cell circuits.

公开(公告)号：US20160351408A1

公开(公告)日：2016-12-01

申请号：US15130515

申请日：2016-04-15

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： BADRO IM ,  YOONCHUL CHO ,  SANGYEOL KANG ,  DAEHYUN KIM ,  DONGKAK LEE ,  JUN-NOH LEE ,  BONGHYUN KIM ,  KONGSOO LEE

IPC分类号： H01L21/308 ,  H01L21/306 ,  H01L21/3065

CPC分类号： H01L21/0337 ,  H01L21/02112 ,  H01L21/02129 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/3086 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32055 ,  H01L21/32139

摘要： Carbon-containing patterns are formed on an etch target layer, side surfaces of the carbon-containing patterns are treated by a hydrophilic process, poly-crystalline silicon spacers are formed on the side surfaces of the carbon-containing patterns after the hydrophilic process has been performed, and the etch target layer is patterned using the poly-crystalline silicon spacers as an etch mask.

摘要翻译： 在蚀刻目标层上形成含碳图案，通过亲水处理处理含碳图案的侧表面，亲水处理已经在含碳图案的侧表面上形成多晶硅间隔物 并且使用多晶硅间隔物作为蚀刻掩模来图案化蚀刻目标层。

公开(公告)号：US20190393225A1

公开(公告)日：2019-12-26

申请号：US16458292

申请日：2019-07-01

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： DONG-HYUN IM ,  DAEHYUN KIM ,  HOON PARK ,  JAE-HONG SEO ,  CHUNHYUNG CHUNG ,  JAE-JOONG CHOI

IPC分类号： H01L27/108 ,  H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L21/283

摘要： A method of fabricating a semiconductor memory device includes etching a substrate that forms a trench that crosses active regions of the substrate, forming a gate insulating layer on bottom and side surfaces of the trench, forming a first gate electrode on the gate insulating layer that fills a lower portion of the trench, oxidizing a top surface of the first gate electrode where a preliminary barrier layer is formed, nitrifying the preliminary barrier layer where a barrier layer is formed, and forming a second gate electrode on the barrier layer that fills an upper portion of the trench.

公开(公告)号：US20190088657A1

公开(公告)日：2019-03-21

申请号：US16050848

申请日：2018-07-31

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： DONG-HYUN IM ,  DAEHYUN KIM ,  HOON PARK ,  JAE-HONG SEO ,  CHUNHYUNG CHUNG ,  JAE-JOONG CHOI

IPC分类号： H01L27/108 ,  H01L21/283 ,  H01L29/423 ,  H01L29/66 ,  H01L29/49 ,  H01L21/28

CPC分类号： H01L27/10823 ,  H01L21/28026 ,  H01L21/28079 ,  H01L21/283 ,  H01L21/82345 ,  H01L27/10814 ,  H01L27/10876 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4958 ,  H01L29/66621

摘要： A method of fabricating a semiconductor memory device includes etching a substrate that forms a trench that crosses active regions of the substrate, forming a gate insulating layer on bottom and side surfaces of the trench, forming a first gate electrode on the gate insulating layer that fills a lower portion of the trench, oxidizing a top surface of the first gate electrode where a preliminary barrier layer is formed, nitrifying the preliminary barrier layer where a barrier layer is formed, and forming a second gate electrode on the barrier layer that fills an upper portion of the trench.

公开(公告)号：US20180113803A1

公开(公告)日：2018-04-26

申请号：US15706967

申请日：2017-09-18

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： DAEHYUN KIM ,  BOKYOUNG KIM ,  SEONGHOON WOO

IPC分类号： G06F12/02 ,  G06F3/06 ,  G11C16/10 ,  G11C16/26

CPC分类号： G06F12/0246 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0679 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32

摘要： A method, executed by a memory controller, of controlling a nonvolatile memory device having first and second planes includes transmitting a first command included in a command queue to the nonvolatile memory device. A block address of a second command is compared with a block address of a third command, when the third command is queued ahead of the second command in the command queue. The second command is selectively transmitted to the nonvolatile memory device prior to the third command based on the comparison result.