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    SEMICONDUCTOR PACKAGE
    1.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20210013189A1

    公开(公告)日：2021-01-14

    申请号：US17036053

    申请日：2020-09-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang-Uk KIM

    IPC: H01L25/10 ,  H01L25/00 ,  H01L23/498

    Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package includes a first semiconductor chip on a first substrate, a first molding layer covering a sidewall of the first semiconductor chip and including at least two guide holes that expose the first substrate and are spaced apart from each other in a periphery of the first substrate, a second substrate on the first molding layer, a connection terminal between the first substrate and the second substrates and connecting the first and second substrates to each other, and an alignment structure that extends from a bottom surface of the second substrate into each of the at least two guide holes of the first molding layer. A height of the alignment structure is greater than a height of the first molding layer and the first semiconductor chip.

    SEMICONDUCTOR PACKAGES AND METHODS OF MANUFACTURING SAME
    3.
    发明申请
    SEMICONDUCTOR PACKAGES AND METHODS OF MANUFACTURING SAME 审中-公开

    公开(公告)号：US20190019758A1

    公开(公告)日：2019-01-17

    申请号：US15956414

    申请日：2018-04-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sang-Uk KIM ,  Sunchul KIM ,  Jinkyeong SEOL ,  BYOUNG WOOK JANG

    IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56

    Abstract: A semiconductor package and a method manufacturing the same are disclosed. At least one semiconductor chip is mounted on a package substrate. An insulative mold layer is formed at sides of the semiconductor chip having at least one recess in a region in which conductive connection members are formed, the recess defining one or more protrusions within the mold layer. An interposer is positioned on the protrusions with the conductive connection members connecting and providing electrical connections between conductive pads on the upper surface of the package and conductive pads on the lower surface of the package substrate. The protrusions may position the interposer in the vertical direction by defining the vertical spacing between the lower surface of the interposer and the upper surface of the package substrate. The protrusions may also position the interposer in one or more horizontal directions and/or prevent substantial movement during connecting of the interposer to the package substrate. An under-fill resin layer may be injected into remaining space between the interposer and the package substrate.

    SEMICONDUCTOR PACKAGE
    4.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20230090461A1

    公开(公告)日：2023-03-23

    申请号：US17723347

    申请日：2022-04-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang-Uk KIM ,  Ki Wook JUNG

    IPC: H01L23/373 ,  H01L25/18 ,  H01L23/538 ,  H01L23/367 ,  H01L49/02

    Abstract: A semiconductor package includes: a substrate; a first semiconductor chip disposed on the substrate; a capacitor disposed on the substrate and spaced apart from the first semiconductor chip in a first direction; an insulating layer disposed on the substrate and covering the capacitor; a first heat conductive layer at least partially surrounding side walls of the first semiconductor chip and disposed on the insulating layer, wherein the first heat conductive layer is in contact with the side walls of the first semiconductor chip, and wherein the first heat conductive layer includes a first material that is a conductive material; and a second heat conductive layer disposed on the first heat conductive layer, wherein the second heat conductive layer is in contact with the first heat conductive layer, wherein the second heat conductive layer includes a second material that is a non-conductive material.

    SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
    5.
    发明申请
    SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME 审中-公开

    公开(公告)号：US20200013764A1

    公开(公告)日：2020-01-09

    申请号：US16249446

    申请日：2019-01-16

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang-Uk KIM

    IPC: H01L25/10 ,  H01L25/00 ,  H01L23/498

    Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package includes a first semiconductor chip on a first substrate, a first molding layer covering a sidewall of the first semiconductor chip and including at least two guide holes that expose the first substrate and are spaced apart from each other in a periphery of the first substrate, a second substrate on the first molding layer, a connection terminal between the first substrate and the second substrates and connecting the first and second substrates to each other, and an alignment structure that extends from a bottom surface of the second substrate into each of the at least two guide holes of the first molding layer. A height of the alignment structure is greater than a height of the first molding layer and the first semiconductor chip.

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