公开(公告)号：US20240321774A1

公开(公告)日：2024-09-26

申请号：US18399519

申请日：2023-12-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kitae Park ,  Chiwan Song ,  Seonkyu Kim ,  Hyunna Bae ,  Seungmin Baek ,  Yongjae Song ,  Joonseok Oh ,  Jaewook Jung ,  Seokil Hong

IPC: H01L23/00 ,  H01L21/02 ,  H01L21/3205 ,  H01L23/31 ,  H01L23/492 ,  H01L25/065 ,  H10B80/00

CPC classification number: H01L23/562 ,  H01L21/0214 ,  H01L21/02249 ,  H01L21/02252 ,  H01L21/32055 ,  H01L23/3135 ,  H01L23/4926 ,  H01L24/48 ,  H01L25/0657 ,  H10B80/00 ,  H01L2224/48149 ,  H01L2224/48227 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2924/3511 ,  H01L2924/3512

Abstract: The present disclosure relates to semiconductor devices and semiconductor packages. One example semiconductor device includes a crystalline silicon layer, an amorphous silicon layer on the crystalline silicon layer and extending along a first surface of the crystalline silicon layer, and a dielectric layer on the amorphous silicon layer and extending along a surface of the amorphous silicon layer. The dielectric layer includes silicon oxynitride and has compressive stress.

公开(公告)号：US20240355709A1

公开(公告)日：2024-10-24

申请号：US18637022

申请日：2024-04-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kitae Park ,  Seonkyu Kim ,  Seungmin Baek ,  Joonseok Oh ,  Joohyung Lee ,  Junghyun Cho

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/544 ,  H01L25/065

CPC classification number: H01L23/481 ,  H01L23/3128 ,  H01L23/544 ,  H01L24/16 ,  H01L25/0657 ,  H01L2223/54426 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/1815

Abstract: A semiconductor package includes a base chip, a first semiconductor chip on the base chip, and a first fillet layer between the base chip and the first semiconductor chip. The base chip includes a base substrate, a plurality of through-electrodes penetrating through the base substrate, a protective layer surrounding the plurality of through-electrodes and covering an upper surface of the base substrate, and a plurality of trenches vertically penetrating the protective layer. The plurality of through-electrodes form a transistor area on the base substrate, and the plurality of trenches include first trenches disposed between adjacent through-vias in the transistor area and second trenches disposed in an outer side portion of the transistor area.