公开(公告)号：US20230133116A1

公开(公告)日：2023-05-04

申请号：US17819231

申请日：2022-08-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Aenee JANG ,  Seungduk BAEK

IPC: H01L25/18 ,  H01L23/48 ,  H01L23/00 ,  H01L23/498

Abstract: A semiconductor package includes a first semiconductor chip including a first semiconductor substrate having an active surface and an inactive surface and a plurality of first through electrodes passing through the first semiconductor substrate. A plurality of second semiconductor chips each includes a second semiconductor substrate having an active surface and an inactive surface. A plurality of second through electrodes passes through the second semiconductor substrate. A plurality of coupling pads is disposed between the first semiconductor chip and the second semiconductor chips. A plurality of chip coupling insulation layers is disposed between the first semiconductor chip and the second semiconductor chips and at least partially surrounds the coupling pads. At least one supporting dummy substrate is stacked on the second semiconductor chips. At least one supporting coupling insulation layer is disposed on a bottom surface of the at least one supporting dummy substrate.

公开(公告)号：US20210143126A1

公开(公告)日：2021-05-13

申请号：US16899013

申请日：2020-06-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongjoo CHOI ,  Seungduk BAEK

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

Abstract: A semiconductor package may include a substrate, a chip stack disposed on the substrate, the chip stack including a plurality of first semiconductor chips vertically stacked on the substrate, a second semiconductor chip disposed on the substrate and horizontally spaced apart from the chip stack, and a third semiconductor chip disposed on the second semiconductor chip. An upper portion of the second semiconductor chip and a lower portion of the third semiconductor chip may contain an insulating element. The upper portion of the second semiconductor chip and the lower portion of the third semiconductor chip may contact each other at an interface between the second semiconductor chip and the third semiconductor chip and may constitute a single object formed of a same material.

公开(公告)号：US20250149430A1

公开(公告)日：2025-05-08

申请号：US18672870

申请日：2024-05-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungduk BAEK

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/48 ,  H01L23/528 ,  H01L25/065 ,  H01L25/18

Abstract: Provided is a semiconductor package including a first semiconductor chip including a substrate, interconnects, an insulating layer on the interconnects, first lower pads on the interconnects, and a first passivation layer on the first lower pads, and a second semiconductor chip including second upper pads contacting the first lower pads, a second passivation layer on the second upper pads and contacting the first passivation layer, second lower pads opposite to the second upper pads, and through-electrodes, wherein the first semiconductor chip has a first longer side extending in a first direction and a first shorter side extending in a second direction, the interconnects include intermediate conductors and connection conductors between the intermediate conductors and the first lower pads, a thickness of the connection conductors is greater than that of the intermediate conductors, and a number of the connection conductors is greater than that of the connection conductors.

公开(公告)号：US20250029895A1

公开(公告)日：2025-01-23

申请号：US18435414

申请日：2024-02-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungduk BAEK

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/065 ,  H10B80/00

Abstract: A semiconductor stacked structure includes a first semiconductor chip including, a central region, an outer region at least partially surrounding the central region, the outer region including a corner region, and a first through-electrode in the central region, a plurality of second semiconductor chips sequentially stacked in the central region and connected to the first semiconductor chip, each of the plurality of second semiconductor chips including a second through-electrode, and at least one passive device in the corner region of the outer region.

公开(公告)号：US20220148994A1

公开(公告)日：2022-05-12

申请号：US17584776

申请日：2022-01-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehyeong KIM ,  Hyeongmun KANG ,  Seungduk BAEK

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/10

Abstract: Disclosed is a semiconductor package comprising a first semiconductor chip and at least one second semiconductor chip on the first semiconductor chip. The second semiconductor chip includes first and second test bumps that are adjacent to an edge of the second semiconductor chip and are on a bottom surface of the second semiconductor chip. The first and second test bumps are adjacent to each other. The second semiconductor chip also includes a plurality of data bumps that are adjacent to a center of the second semiconductor chip and are on the bottom surface of the second semiconductor chip. A first interval between the second test bump and one of the data bumps is greater than a second interval between the first test bump and the second test bump. The one of the data bumps is most adjacent to the second test bump.

公开(公告)号：US20210066231A1

公开(公告)日：2021-03-04

申请号：US16846616

申请日：2020-04-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yunrae CHO ,  Jinyeol YANG ,  Jungmin KO ,  Seungduk BAEK

IPC: H01L23/00

Abstract: An integrated circuit device includes a wiring structure, first and second inter-wiring insulating layers, redistributions patterns and a cover insulating layer. The wiring structure includes wiring layers having a multilayer wiring structure and via plugs. The first inter-wiring insulating layer that surrounds the wiring structure on a substrate. The second inter-wiring insulating layer is on the first inter-wiring insulating layer, and redistribution via plugs are connected to the wiring structure through the second inter-wiring insulating layer. The redistribution patterns includes pad patterns and dummy patterns on the second inter-wiring insulating layer. Each patterns has a thickness greater than a thickness of each wiring layer. The cover insulating layer covers some of the redistribution patterns. The dummy patterns are in the form of lines that extend in a horizontal direction parallel to the substrate.

公开(公告)号：US20250149444A1

公开(公告)日：2025-05-08

申请号：US18674339

申请日：2024-05-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungduk BAEK

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/48 ,  H01L25/10

Abstract: A semiconductor package includes at least one first interconnecting conductor in contact with at least one first pad, and first peripheral conductors on opposites sides of the at least one first interconnecting conductor, the first peripheral conductors extending in a first horizontal direction. The semiconductor package further includes at least one second interconnecting conductor in contact with the at least one second pad, and second peripheral conductors on opposite sides of the at least one second interconnecting conductor, the second peripheral conductors extending in a second horizontal direction, intersecting the first horizontal direction. In a plan view, first overlapping regions, in which the first peripheral conductors overlap with the second peripheral conductors, are spaced apart from each other in the first horizontal direction and the second horizontal direction

公开(公告)号：US20210343616A1

公开(公告)日：2021-11-04

申请号：US16953745

申请日：2020-11-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongjoo CHOI ,  Seungduk BAEK ,  Youngdeuk KIM

IPC: H01L23/367 ,  H01L25/065 ,  H01L23/522

Abstract: Provided is a semiconductor package including a lower semiconductor chip including a lower semiconductor substrate, a rear surface protecting layer covering a non-active surface of the lower semiconductor substrate, a plurality of lower via electrodes, and a plurality of rear surface signal pads and a plurality of rear surface thermal pads arranged on the rear surface protecting layer; an upper semiconductor chip including an upper semiconductor substrate, a wiring structure on an active surface of the upper semiconductor substrate, a front surface protecting layer that covers the wiring structure and has a plurality of front surface openings, and a plurality of signal vias and a plurality of thermal vias that fill the front surface openings; and a plurality of signal bumps connecting between the rear surface signal pads and the signal vias and a plurality of thermal bumps connecting between the rear surface thermal pads and the thermal vias.

公开(公告)号：US20210175134A1

公开(公告)日：2021-06-10

申请号：US17010059

申请日：2020-09-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehyeong KIM ,  Hyeongmun KANG ,  Seungduk BAEK

IPC: H01L21/66 ,  H01L23/00 ,  H01L25/18

Abstract: Disclosed is a semiconductor package comprising a first semiconductor chip and at least one second semiconductor chip on the first semiconductor chip. The second semiconductor chip includes first and second test bumps that are adjacent to an edge of the second semiconductor chip and are on a bottom surface of the second semiconductor chip. The first and second test bumps are adjacent to each other. The second semiconductor chip also includes a plurality of data bumps that are adjacent to a center of the second semiconductor chip and are on the bottom surface of the second semiconductor chip. A first interval between the second test bump and one of the data bumps is greater than a second interval between the first test bump and the second test bump. The one of the data bumps is most adjacent to the second test bump.

公开(公告)号：US20160093541A1

公开(公告)日：2016-03-31

申请号：US14714667

申请日：2015-05-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungduk BAEK ,  Ji Hwang KIM ,  Taeje CHO

IPC: H01L21/66 ,  H01L23/525 ,  H01L21/768 ,  G01R31/26

CPC classification number: H01L22/14 ,  G01R31/2601 ,  H01L22/32 ,  H01L23/5256 ,  H01L24/06 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor package includes providing a semiconductor chip including a circuit pattern, a connection pad, a first test pad and a second test pad, each of the connection pad, the first test pad and the second test pad respectively electrically connected to the circuit pattern, evaluating electrical characteristics of the semiconductor chip by applying a first test voltage to the first test pad and a second test voltage to the second test pad, the second test voltage being higher than the first test voltage, and electrically disconnecting the second test pad from the circuit pattern.

Abstract translation: 制造半导体封装的方法包括提供包括电路图案的半导体芯片，连接焊盘，第一测试焊盘和第二测试焊盘，每个连接焊盘，第一测试焊盘和第二测试焊盘分别电连接到 所述电路图案，通过向所述第一测试焊盘施加第一测试电压和对所述第二测试焊盘施加第二测试电压来评估所述半导体芯片的电特性，所述第二测试电压高于所述第一测试电压，并且电连接所述第二测试电压 测试板从电路图案。