公开(公告)号：US20240250072A1

公开(公告)日：2024-07-25

申请号：US18492170

申请日：2023-10-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngdeuk KIM

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/3107 ,  H01L23/481 ,  H01L23/49894 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0652 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438

Abstract: A semiconductor package includes a first semiconductor chip including a substrate having a front surface and an opposite rear surface, a rear protective layer on the rear surface, a plurality of first and second rear through-vias penetrating through the rear protective layer and extending into the substrate, a plurality of front through-vias extending from the front surface and connected to the first rear through-vias, and a plurality of rear pads on the rear protective layer and connected to the plurality of first and second rear through-vias. A second semiconductor chip is on the first semiconductor chip, and includes a plurality of front pads electrically connected to the plurality of rear pads by respective bump structures. Each of the plurality of rear through-vias has a width greater than a width of each of the plurality of front through-vias.

公开(公告)号：US20240194643A1

公开(公告)日：2024-06-13

申请号：US18524094

申请日：2023-11-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngdeuk KIM

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/03462 ,  H01L2224/05155 ,  H01L2224/0603 ,  H01L2224/06519 ,  H01L2224/1358 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/1403 ,  H01L2224/14519 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/17519 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/181

Abstract: A semiconductor package includes: a first semiconductor chip including a first substrate, first through electrodes, first signal bonding pads electrically connected to the first through electrodes, and first dummy bonding pads electrically insulated from the first through electrodes, wherein the first through electrodes penetrate the first substrate; a second semiconductor chip stacked on the first semiconductor chip and including a second substrate and a plurality of second chip pads on the second substrate and respectively corresponding to the first signal bonding pads and the first dummy bonding pads; first conductive bumps between the first signal bonding pads and the corresponding second chip pads; and second conductive bumps between the first dummy bonding pads and the corresponding second chip pads, wherein the first conductive bumps include a signal bump pad and a first solder bump, and the second conductive bumps include a thermal bump pad and a second solder bump.

公开(公告)号：US20240186290A1

公开(公告)日：2024-06-06

申请号：US18236024

申请日：2023-08-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taehwan KIM ,  Youngdeuk KIM ,  Jaechoon KIM ,  Kyungsuk OH ,  Jonggyu LEE ,  Mina CHOI

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/522

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06541

Abstract: A semiconductor package includes electrically connected first to third semiconductor chips, stacked in a vertical direction; an encapsulant on the first semiconductor chip and encapsulating a portion of each of the semiconductor chips; and external connection bumps below the first semiconductor chip and being electrically connected to the semiconductor chips, wherein the semiconductor chips each include a plurality of lower pads, the first and second semiconductor chips each include a plurality of upper pads including a first group of upper pads and a second group of upper pads, and through-electrodes electrically respectively connecting the upper pads and the lower pads, and the through-electrodes include a first group of through-electrodes respectively connected to the first group of upper pads, and a second group of through-electrodes connected to upper pads that are electrically connected to each other of the second group of upper pads.

公开(公告)号：US20240162115A1

公开(公告)日：2024-05-16

申请号：US18218322

申请日：2023-07-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngdeuk KIM

IPC: H01L23/467 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/467 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0652 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/1431

Abstract: A semiconductor package includes: a first semiconductor chip; a plurality of second semiconductor chips sequentially stacked on the first semiconductor chip, the plurality of second semiconductor chips including an uppermost semiconductor chip including a central region and a peripheral region at a periphery of the central region; at least one first temperature sensor provided on an upper surface of the uppermost semiconductor chip in the central region; a plurality of second temperature sensors provided on the upper surface in the peripheral region; and a thermal conductive member provided on the uppermost semiconductor chip and covering the at least one first temperature sensor and the plurality of second temperature sensors.

公开(公告)号：US20210343616A1

公开(公告)日：2021-11-04

申请号：US16953745

申请日：2020-11-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongjoo CHOI ,  Seungduk BAEK ,  Youngdeuk KIM

IPC: H01L23/367 ,  H01L25/065 ,  H01L23/522

Abstract: Provided is a semiconductor package including a lower semiconductor chip including a lower semiconductor substrate, a rear surface protecting layer covering a non-active surface of the lower semiconductor substrate, a plurality of lower via electrodes, and a plurality of rear surface signal pads and a plurality of rear surface thermal pads arranged on the rear surface protecting layer; an upper semiconductor chip including an upper semiconductor substrate, a wiring structure on an active surface of the upper semiconductor substrate, a front surface protecting layer that covers the wiring structure and has a plurality of front surface openings, and a plurality of signal vias and a plurality of thermal vias that fill the front surface openings; and a plurality of signal bumps connecting between the rear surface signal pads and the signal vias and a plurality of thermal bumps connecting between the rear surface thermal pads and the thermal vias.

公开(公告)号：US20240079393A1

公开(公告)日：2024-03-07

申请号：US18218673

申请日：2023-07-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngdeuk KIM ,  Heejung HWANG

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L23/538 ,  H10B80/00

CPC classification number: H01L25/105 ,  H01L23/3135 ,  H01L23/3675 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H10B80/00 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/15153 ,  H01L2924/15174

Abstract: A semiconductor package includes a package substrate including a substrate cavity, the substrate cavity extending from an upper surface of the package substrate toward a lower surface of the package substrate, a wiring interposer attached to the package substrate, a memory semiconductor structure attached to a lower surface of the wiring interposer, at least a portion of the memory semiconductor structure art being accommodated in the substrate cavity, a logic semiconductor chip attached to an upper surface of the wiring interposer, a conductive spacer spaced apart from the logic semiconductor chip in a horizontal direction, the conductive spacer being attached to the upper surface of the wiring interposer and overlapping the memory semiconductor structure in a vertical direction, and a heat dissipation member over the logic semiconductor chip and the conductive spacer.

公开(公告)号：US20240014166A1

公开(公告)日：2024-01-11

申请号：US18218886

申请日：2023-07-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngdeuk KIM ,  Jaechoon KIM ,  Taehwan KIM ,  Kyungsuk OH ,  Heejung Hwang

IPC: H01L23/00 ,  H01L25/18 ,  H10B80/00 ,  H01L25/00

CPC classification number: H01L24/73 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/33 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/18 ,  H10B80/00 ,  H01L25/50 ,  H01L2224/05025 ,  H01L2224/05155 ,  H01L2224/05073 ,  H01L2224/05564 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05666 ,  H01L2224/06181 ,  H01L2224/05647 ,  H01L2224/80359 ,  H01L2924/0544 ,  H01L2924/059 ,  H01L2224/06505 ,  H01L2224/08145 ,  H01L2224/13111 ,  H01L2224/13109 ,  H01L2224/13113 ,  H01L2224/1312 ,  H01L2224/13147 ,  H01L2224/13139 ,  H01L2224/13118 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2924/014 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32013 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/80357 ,  H01L2224/81203 ,  H01L2224/83203 ,  H01L2224/9211 ,  H01L2224/92222 ,  H01L2224/92242 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/9222

Abstract: A semiconductor package including: a lower chip; a chip structure including stacked semiconductor chips; and an adhesive film, the semiconductor chips include first bonding chips bonded to each other by bumps and second bonding chips directly bonded to each other, the first bonding chips include: a first bonding lower chip including a first bonding upper pad; and a first bonding upper chip on the first bonding lower chip and including a first bonding lower pad, the second bonding chips include: a second bonding lower chip including a second bonding upper insulating layer and a second bonding upper pad; and a second bonding upper chip on the second bonding lower chip and including a second bonding lower insulating layer, and a second bonding lower pad, and the adhesive film surrounds side surfaces of the bumps, fills a region between the first bonding lower and upper chips, and protrudes from the region.