公开(公告)号：US09859022B2

公开(公告)日：2018-01-02

申请号：US14722823

申请日：2015-05-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-joong Kim ,  Soo-hyeong Kim ,  Sang-hoon Shin ,  Ju-yun Jung ,  Ho-young Song ,  Kyo-min Sohn ,  Hae-suk Lee ,  Bu-il Jung ,  Han-vit Jeong

IPC: G06F11/10 ,  G11C29/52 ,  G11C29/04

CPC classification number: G11C29/52 ,  G06F11/1048 ,  G11C2029/0411

Abstract: A memory device including: an error correction code (ECC) cell array; an ECC engine configured to receive write data to be written to a memory cell array and generate internal parity bits for the write data; and an ECC select unit configured to receive the internal parity bits and external parity bits and, in response to a first level of a control signal, store the internal parity bits in the ECC cell array and, in response to a second level of the control signal store the external parity bits in the ECC cell array.