公开(公告)号：US09859022B2

公开(公告)日：2018-01-02

申请号：US14722823

申请日：2015-05-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-joong Kim ,  Soo-hyeong Kim ,  Sang-hoon Shin ,  Ju-yun Jung ,  Ho-young Song ,  Kyo-min Sohn ,  Hae-suk Lee ,  Bu-il Jung ,  Han-vit Jeong

IPC: G06F11/10 ,  G11C29/52 ,  G11C29/04

CPC classification number: G11C29/52 ,  G06F11/1048 ,  G11C2029/0411

Abstract: A memory device including: an error correction code (ECC) cell array; an ECC engine configured to receive write data to be written to a memory cell array and generate internal parity bits for the write data; and an ECC select unit configured to receive the internal parity bits and external parity bits and, in response to a first level of a control signal, store the internal parity bits in the ECC cell array and, in response to a second level of the control signal store the external parity bits in the ECC cell array.

公开(公告)号：US10783979B2

公开(公告)日：2020-09-22

申请号：US16274396

申请日：2019-02-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-ho Ok ,  Pyung-moon Zhang ,  Sang-hoon Shin ,  Ki-hyun Park ,  Yong-sik Park

IPC: G11C29/00 ,  G11C29/38 ,  G11C29/36 ,  G11C29/50

Abstract: A built-in self-test (BIST) circuit and a method of operating BIST circuit is disclosed. The BIST circuit is configured to generate a test pattern based on a plurality of test parameters including a first test parameter and a second test parameter and perform a test on at least one memory core. The method includes setting a sweep range comprising a sweep start point of the first test parameter and a sweep end point thereof; generating a first test pattern corresponding to each sweep point of the sweep range from the sweep start point of the first test parameter and the sweep end point thereof and providing the first test pattern to the at least one memory core; receiving output data corresponding to the first test pattern from the at least one memory core and comparing the output data and a predetermined reference data; and generating first test result information based on results of the comparing.

公开(公告)号：US20190180837A1

公开(公告)日：2019-06-13

申请号：US16274396

申请日：2019-02-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-ho Ok ,  Pyung-moon Zhang ,  Sang-hoon Shin ,  Ki-hyun Park ,  Yong-sik Park

IPC: G11C29/38 ,  G11C29/50 ,  G11C29/36

CPC classification number: G11C29/38 ,  G11C29/36 ,  G11C29/50012 ,  G11C2029/3602 ,  G11C2029/5004

Abstract: A built-in self-test (BIST) circuit and a method of operating BIST circuit is disclosed. The BIST circuit is configured to generate a test pattern based on a plurality of test parameters including a first test parameter and a second test parameter and perform a test on at least one memory core. The method includes setting a sweep range comprising a sweep start point of the first test parameter and a sweep end point thereof; generating a first test pattern corresponding to each sweep point of the sweep range from the sweep start point of the first test parameter and the sweep end point thereof and providing the first test pattern to the at least one memory core; receiving output data corresponding to the first test pattern from the at least one memory core and comparing the output data and a predetermined reference data; and generating first test result information based on results of the comparing.

公开(公告)号：US20170162276A1

公开(公告)日：2017-06-08

申请号：US15262027

申请日：2016-09-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-ho Ok ,  Pyung-moon Zhang ,  Sang-hoon Shin ,  Ki-hyun Park ,  Yong-sik Park

IPC: G11C29/38 ,  G11C29/36

CPC classification number: G11C29/38 ,  G11C29/36 ,  G11C29/50012 ,  G11C2029/3602 ,  G11C2029/5004

Abstract: A built-in self-test (BIST) circuit and a method of operating BIST circuit is disclosed. The BIST circuit is configured to generate a test pattern based on a plurality of test parameters including a first test parameter and a second test parameter and perform a test on at least one memory core. The method includes setting a sweep range comprising a sweep start point of the first test parameter and a sweep end point thereof; generating a first test pattern corresponding to each sweep point of the sweep range from the sweep start point of the first test parameter and the sweep end point thereof and providing the first test pattern to the at least one memory core; receiving output data corresponding to the first test pattern from the at least one memory core and comparing the output data and a predetermined reference data; and generating first test result information based on results of the comparing.

公开(公告)号：US10210948B2

公开(公告)日：2019-02-19

申请号：US15262027

申请日：2016-09-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-ho Ok ,  Pyung-moon Zhang ,  Sang-hoon Shin ,  Ki-hyun Park ,  Yong-sik Park

IPC: G11C29/00 ,  G11C29/38 ,  G11C29/36 ,  G11C29/50

Abstract: A built-in self-test (BIST) circuit and a method of operating BIST circuit is disclosed. The BIST circuit is configured to generate a test pattern based on a plurality of test parameters and perform a test on at least one memory core. The method includes setting a sweep range including a sweep start point of a first test parameter and a sweep end point thereof; generating a first test pattern corresponding to each sweep point of the sweep range from the sweep start point of the first test parameter and the sweep end point thereof and providing the first test pattern to the at least one memory core; receiving output data corresponding to the first test pattern from the at least one memory core and comparing the output data and a predetermined reference data; and generating first test result information based on results of the comparing.