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公开(公告)号：US11521046B2
公开(公告)日：2022-12-06
申请号：US16170081
申请日：2018-10-25
发明人： Sungho Kim , Jinseok Kim , Yulhwa Kim , Jaejoon Kim , Dusik Park , Hyungjun Kim
摘要： A method of performing operations on a plurality of inputs and a same kernel using a delay time by using a same processor, and a neural network device thereof are provided, the neural network device includes input data including a first input and a second input, and a processor configured to obtain a first result by performing operations between the first input and a plurality of kernels, to obtain a second result by performing operations between the second input, which is received at a time delayed by a first interval from a time when the first input is received, and the plurality of kernels, and to obtain output data using the first result and the second result. The neural network device may include neuromorphic hardware and may perform convolutional neural network (CNN) mapping.
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公开(公告)号：US11681899B2
公开(公告)日：2023-06-20
申请号：US16561378
申请日：2019-09-05
发明人： Sungho Kim , Yulhwa Kim , Hyungjun Kim , Jae-Joon Kim , Jinseok Kim
摘要： A method of implementing a neural network in a neuromorphic apparatus having a memory and processing circuitry, where the method includes dividing, by the processing circuitry, the neural network into a plurality of sub-networks based on a size of a core of the memory to implement the neural network, initializing, by the processing circuitry, a hyper-parameter used in the sub-networks, and training, by the processing circuitry, the sub-networks by using the hyper-parameter.
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公开(公告)号：US20200012925A1
公开(公告)日：2020-01-09
申请号：US16454881
申请日：2019-06-27
发明人： JAE-JOON KIM , Jinseok Kim , Taesu Kim
摘要： A neuromorphic system includes an address translation device that translates an address corresponding to each of synaptic weights between presynaptic neurons and postsynaptic neurons to generate a translation address, and a plurality of synapse memories that store the synaptic weights based on the translation address. The translation address is generated such that at least two of synaptic weights corresponding to each of the postsynaptic neurons are stored in different synapse memories of the plurality of synapse memories and such that at least two of synaptic weights corresponding to each of the presynaptic neurons are stored in different synapse memories.
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4.发明授权公开(公告)号：US11340781B2
公开(公告)日：2022-05-24
申请号：US16795334
申请日：2020-02-19
发明人： Seokwon Kim , Jinseok Kim , Dami Jeon
IPC分类号： G06F3/041 , G06F3/04886
摘要： An electronic device includes a display, at least one processor, and a memory. The memory is configured to store instructions that when executed enable the processor to control the display to display an execution screen of application stored in the memory. The instructions also enable the processor to identify an occurrence of an event for displaying an execution screen of the virtual keyboard application while displaying the execution screen of the application. The instructions further enable the processor to, based on the occurrence of the event, identify at least one color value related to the at least one element included in the execution screen of the application, and control the display to display the execution screen of the virtual keyboard application corresponding to the at least one identified color value.
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公开(公告)号：US12125524B2
公开(公告)日：2024-10-22
申请号：US18303309
申请日：2023-04-19
发明人： Jinseok Kim , Yulhwa Kim , Jae-Joon Kim , Hyungjun Kim
IPC分类号： G11C11/412 , G06N3/08 , G11C11/418 , G11C11/419
CPC分类号： G11C11/412 , G06N3/08 , G11C11/418 , G11C11/419
摘要： Disclosed are a first memory cell, a second memory cell, and a summing circuit. The first memory cell outputs only one of a first voltage through a first bit line and a second voltage through a second bit line, based on first input data received through a first word line and a second word line and a first weight. The second memory cell outputs only one of a third voltage through the first bit line and a fourth voltage through the second bit line, based on second input data received through a third word line and a fourth word line and a second weight; and the summing circuit generates an output voltage having a level corresponding to a sum of a level of a voltage received through the first bit line and a level of a voltage received through the second bit line.
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6.发明授权公开(公告)号：US11797221B2
公开(公告)日：2023-10-24
申请号：US17473062
申请日：2021-09-13
发明人： Sumin Ahn , Jinseok Kim , Jungjeong Jo
IPC分类号： G06F3/06
CPC分类号： G06F3/0655 , G06F3/0604 , G06F3/0679
摘要： In a method of operating a storage device, a first throughput, for transmitting a plurality of write command completion responses to an external host device, is set to an initial value. The plurality of write command completion responses represent an execution of a plurality of write commands received from the external host device. The plurality of write commands are executed. The plurality of write command completion responses are transmitted to the external host device based on the first throughput that is set to the initial value. A plurality of write data are internally stored based on the plurality of write commands. A second throughput, associated with an operation of internally storing the plurality of write data, is monitored during a predetermined first time interval. The first throughput is changed based on the second throughput that is monitored during the predetermined first time interval.
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公开(公告)号：US11790985B2
公开(公告)日：2023-10-17
申请号：US17723358
申请日：2022-04-18
发明人： Jinseok Kim , Yulhwa Kim , Jae-Joon Kim , Hyungjun Kim
IPC分类号： G11C11/412 , G11C11/418 , G11C11/419 , G06N3/08
CPC分类号： G11C11/412 , G06N3/08 , G11C11/418 , G11C11/419
摘要： Disclosed are a first memory cell, a second memory cell, and an amplification circuit. The first memory cell outputs a first voltage through a first bit line or a second voltage through a second bit line, based on first input data received through a first word line and a second word line and a first weight. The second memory cell outputs a third voltage through the first bit line or a fourth voltage through the second bit line, based on second input data received through a third word line and a fourth word line and a second weight. The amplification circuit generates an output voltage having a level corresponding to a sum of a level of a voltage received through the first bit line and a level of a voltage received through the second bit line.
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公开(公告)号：US11556765B2
公开(公告)日：2023-01-17
申请号：US16454881
申请日：2019-06-27
发明人： Jae-Joon Kim , Jinseok Kim , Taesu Kim
摘要： A neuromorphic system includes an address translation device that translates an address corresponding to each of synaptic weights between presynaptic neurons and postsynaptic neurons to generate a translation address, and a plurality of synapse memories that store the synaptic weights based on the translation address. The translation address is generated such that at least two of synaptic weights corresponding to each of the postsynaptic neurons are stored in different synapse memories of the plurality of synapse memories and such that at least two of synaptic weights corresponding to each of the presynaptic neurons are stored in different synapse memories.
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9.发明授权公开(公告)号：US11449219B2
公开(公告)日：2022-09-20
申请号：US16857692
申请日：2020-04-24
发明人： Seungyup Lee , Jinseok Kim , Minjeong Moon , Minjung Moon , Myojin Bang , Seoyoung Yoon , Dami Jeon , Jaegi Han , Jiyoon Heo
IPC分类号： G06F3/04883 , G06F3/0481
摘要： Disclosed is an electronic device including a display device including a touch sensor and a processor electrically connected to the touch sensor and the display device, wherein the processor is configured to control the electronic device to: display content and a cursor on a first area of the display device, display a touch pad user interface configured to receive a touch input on a second area of the display device, and control the cursor on the first area based on the touch input received through the touch pad user interface displayed on the second area.
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10.发明授权公开(公告)号：US11119693B2
公开(公告)日：2021-09-14
申请号：US16810478
申请日：2020-03-05
发明人： Sumin Ahn , Jinseok Kim , Jungjeong Jo
IPC分类号： G06F3/06
摘要： In a method of operating a storage device, a first throughput, for transmitting a plurality of write command completion responses to an external host device, is set to an initial value. The plurality of write command completion responses represent an execution of a plurality of write commands received from the external host device. The plurality of write commands are executed. The plurality of write command completion responses are transmitted to the external host device based on the first throughput that is set to the initial value. A plurality of write data are internally stored based on the plurality of write commands. A second throughput, associated with an operation of internally storing the plurality of write data, is monitored during a predetermined first time interval. The first throughput is changed based on the second throughput that is monitored during the predetermined first time interval.
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