公开(公告)号：US20230171963A1

公开(公告)日：2023-06-01

申请号：US17883272

申请日：2022-08-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungun Lee ,  Inmo Kim ,  Sujeong Kim

IPC: H01L27/11573 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  G11C5/06

CPC classification number: H01L27/11573 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  G11C5/06

Abstract: A semiconductor device includes a memory cell region including a plurality of memory cells disposed on a first semiconductor substrate and including gate electrodes stacked to be spaced apart from each other on the first semiconductor substrate and channel structures passing through the gate electrodes and connected to the first semiconductor substrate, a peripheral circuit region including a first conductivity-type impurity, disposed on a second semiconductor substrate having an upper surface facing each other in a first direction, perpendicular to an upper surface of the first semiconductor substrate, and including peripheral circuits controlling the plurality of memory cells, wherein the peripheral circuits include a plurality of well regions formed in the second semiconductor substrate, an ion implantation region disposed between the plurality of well regions and including the first conductivity-type impurity, and a plurality of antenna diodes, and at least one of the plurality of antenna diodes overlaps the ion implantation region in the first direction. Accordingly, in the semiconductor device according to an exemplary embodiment of the present inventive concept, an antenna diode may be inserted, while minimizing an increase in an interval between the plurality of well regions, and further, peripheral circuits may be integrated and wiring complexity may be reduced.

公开(公告)号：US20240306394A1

公开(公告)日：2024-09-12

申请号：US18434356

申请日：2024-02-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungun Lee ,  Pansuk Kwak ,  Changyeon Yu

IPC: H10B43/40 ,  G11C16/08 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

CPC classification number: H10B43/40 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  G11C16/08

Abstract: A memory device includes a stack structure, in which a common source line is formed, and a peripheral circuit structure overlapping the stack structure when viewed in plan view and comprising a common source line driver configured to discharge the common source line. The common source line driver includes a first common source line driving unit, electrically connected to the common source line through a first network and configured to discharge the common source line, and a second common source line driving unit electrically connected to the common source line through a second network, different from the first network, and configured to discharge the common source line. The first common source line driving unit and the second common source line driving unit are controlled independently of each other.