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公开(公告)号：US11670591B2
公开(公告)日：2023-06-06
申请号：US17404757
申请日：2021-08-17
发明人： In-Hyuk Choi , Wonchul Lee , Joonhyoung Yang
IPC分类号： H01L23/48 , H01L23/52 , H01L23/528 , H01L29/06 , H01L23/522
CPC分类号： H01L23/528 , H01L23/5226 , H01L29/0649
摘要： A semiconductor device includes; a semiconductor substrate including a first region and a second region, a first interlayer insulating layer on the second region, a capping layer disposed on the first interlayer insulating layer, an upper surface of the capping layer includes a first trench, conductive patterns spaced apart on the capping layer, side surfaces of the conductive patterns are aligned with inner side surfaces of the first trench, and a peripheral separation pattern disposed in the first trench to cover the side surfaces of the conductive patterns. The peripheral separation pattern has a first thickness on the side surfaces of the conductive patterns and a second thickness greater than or equal to the first thickness on a lower surface.
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公开(公告)号：US10347641B2
公开(公告)日：2019-07-09
申请号：US15814824
申请日：2017-11-16
发明人： Jihoon Kim , Wonchul Lee
IPC分类号： H01L27/108 , H01L49/02
摘要： A semiconductor device includes a substrate including a cell region and peripheral region and bottom electrodes on the substrate. The bottom electrodes are arranged in a first row and a second row each extending in a first direction. The first row and the second row are adjacent to each other in a second direction perpendicular to the first direction. The bottom electrodes in the first row include an outermost bottom electrode and a next outermost bottom electrode that are separated by a first distance in the first direction. The bottom electrodes in the second row include an outermost bottom electrode and a next outermost bottom electrode that are separated by a second distance in the first direction. The outermost bottom electrode in the first row is on the peripheral region of the substrate. The outermost bottom electrode in the second row is on the cell region of the substrate.
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公开(公告)号：US20240206157A1
公开(公告)日：2024-06-20
申请号：US18592121
申请日：2024-02-29
发明人： Hyejin Seong , Dongsoo Woo , Wonchul Lee
IPC分类号： H10B12/00
CPC分类号： H10B12/34 , H10B12/053 , H10B12/09 , H10B12/315 , H10B12/482 , H10B12/485 , H10B12/50
摘要： A semiconductor memory device includes a substrate having a memory cell region where a plurality of active regions are defined; a word line having a stack structure of a lower word line layer and an upper word line layer and extending over the plurality of active regions in a first horizontal direction, and a buried insulation layer on the word line; a bit line structure arranged on the plurality of active regions, extending in a second horizontal direction perpendicular to the first horizontal direction, and having a bit line; and a word line contact plug electrically connected to the lower word line layer by penetrating the buried insulation layer and the upper word line layer and having a plug extension in an upper portion of the word line contact plug, the plug extension having a greater horizontal width than a lower portion of the word line contact plug.
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公开(公告)号：US11917812B2
公开(公告)日：2024-02-27
申请号：US17484679
申请日：2021-09-24
发明人： Sohyeon Bae , Wonchul Lee , Jaehyun Kim , Jaehyuk Jang , Hyebin Choi
IPC分类号： H10B12/00 , H01L23/528
CPC分类号： H10B12/315 , H01L23/528
摘要： A semiconductor device includes a gate structure and a contact plug. The gate structure extends in a first direction parallel to the substrate, and includes a first conductive pattern, a second conductive pattern and a gate mask sequentially stacked. The contact plug contacts an end portion in the first direction of the gate structure, and includes a first extension portion extending in a vertical direction and contacting sidewalls of the gate mask and the second conductive pattern, a second extension portion under and contacting the first extension portion and a sidewall of the first conductive pattern, and a protrusion portion under and contacting the second extension portion. A bottom of the protrusion portion does not contact the first conductive pattern. A first slope of a sidewall of the first extension portion is greater than a second slope of a sidewall of the second extension portion.
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5.发明申请MEMORY CONTROLLER, METHOD OF OPERATING THE SAME AND MEMORY SYSTEM INCLUDING THE SAME 有权存储器控制器，其操作方法和包括其的存储器系统公开(公告)号：US20140237165A1
公开(公告)日：2014-08-21
申请号：US14081371
申请日：2013-11-15
发明人： YOUNGIL SEO , Jungho Yun , Wonchul Lee , Dawoon Jung
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F2212/1032 , G06F2212/7205
摘要： A memory controller controlling a nonvolatile memory device having a plurality of memory blocks as a data storage space includes an error detection and correction circuit and a reclaim control unit. The error detection and correction circuit receives data from a memory block and calculates a comparison result by comparing a bit error rate of the received data and a predetermined value. The reclaim control unit determines whether or not to perform a read reclaim operation depending on the comparison result and a read voltage used to read the data. The read reclaim operation copies the data to a memory block different from a memory block having stored the data.
摘要翻译： 控制具有多个存储块作为数据存储空间的非易失性存储器件的存储器控制器包括错误检测和校正电路以及回收控制单元。 误差检测和校正电路从存储器块接收数据，并通过比较接收到的数据的误码率和预定值来计算比较结果。 回收控制单元根据比较结果和用于读取数据的读取电压来确定是否执行读取回收操作。 读回收操作将数据复制到与存储数据的存储块不同的存储器块。
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公开(公告)号：US20220231027A1
公开(公告)日：2022-07-21
申请号：US17716194
申请日：2022-04-08
发明人： Hyejin Seong , Dongsoo Woo , Wonchul Lee
IPC分类号： H01L27/108
摘要： A semiconductor memory device includes a substrate having a memory cell region where a plurality of active regions are defined; a word line having a stack structure of a lower word line layer and an upper word line layer and extending over the plurality of active regions in a first horizontal direction, and a buried insulation layer on the word line; a bit line structure arranged on the plurality of active regions, extending in a second horizontal direction perpendicular to the first horizontal direction, and having a bit line; and a word line contact plug electrically connected to the lower word line layer by penetrating the buried insulation layer and the upper word line layer and having a plug extension in an upper portion of the word line contact plug, the plug extension having a greater horizontal width than a lower portion of the word line contact plug.
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公开(公告)号：US20210193664A1
公开(公告)日：2021-06-24
申请号：US16993394
申请日：2020-08-14
发明人： Hyejin Seong , Dongsoo Woo , Wonchul Lee
IPC分类号： H01L27/108
摘要： A semiconductor memory device includes a substrate having a memory cell region where a plurality of active regions are defined; a word line having a stack structure of a lower word line layer and an upper word line layer and extending over the plurality of active regions in a first horizontal direction, and a buried insulation layer on the word line; a bit line structure arranged on the plurality of active regions, extending in a second horizontal direction perpendicular to the first horizontal direction, and having a bit line; and a word line contact plug electrically connected to the lower word line layer by penetrating the buried insulation layer and the upper word line layer and having a plug extension in an upper portion of the word line contact plug, the plug extension having a greater horizontal width than a lower portion of the word line contact plug.
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公开(公告)号：US10340277B2
公开(公告)日：2019-07-02
申请号：US15712479
申请日：2017-09-22
发明人： Jae-Hoon Song , Kiheum Nam , Wonchul Lee
IPC分类号： H01L27/108 , H01L29/41 , H01L21/768 , H01L23/528 , H01L49/02 , H01L27/02
摘要： A semiconductor device includes a plurality of pillar structures on a semiconductor substrate, and a support pattern in contact with at least a part of each of the pillar structures, the support pattern connecting the pillar structures with one another, wherein the support pattern includes support holes exposing side surfaces of the pillar structures, the support holes including at least a first support hole and a second support hole that are spaced apart from each other, the first and second support holes having different shapes from each other.
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9.发明授权Memory controller, method of operating the same and memory system including the same 有权内存控制器，操作方法和包含相同的内存系统公开(公告)号：US09519576B2
公开(公告)日：2016-12-13
申请号：US14081371
申请日：2013-11-15
发明人： Youngil Seo , Jungho Yun , Wonchul Lee , Dawoon Jung
CPC分类号： G06F12/0246 , G06F2212/1032 , G06F2212/7205
摘要： A memory controller controlling a nonvolatile memory device having a plurality of memory blocks as a data storage space includes an error detection and correction circuit and a reclaim control unit. The error detection and correction circuit receives data from a memory block and calculates a comparison result by comparing a bit error rate of the received data and a predetermined value. The reclaim control unit determines whether or not to perform a read reclaim operation depending on the comparison result and a read voltage used to read the data. The read reclaim operation copies the data to a memory block different from a memory block having stored the data.
摘要翻译： 控制具有多个存储块作为数据存储空间的非易失性存储器件的存储器控制器包括错误检测和校正电路以及回收控制单元。 误差检测和校正电路从存储器块接收数据，并通过比较接收到的数据的误码率和预定值来计算比较结果。 回收控制单元根据比较结果和用于读取数据的读取电压来确定是否执行读取回收操作。 读回收操作将数据复制到与存储数据的存储块不同的存储器块。
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公开(公告)号：US09348708B2
公开(公告)日：2016-05-24
申请号：US14172948
申请日：2014-02-05
发明人： Dawoon Jung , Jungho Yun , Min-Chul Kim , Youngil Seo , Wonchul Lee
CPC分类号： G06F11/1666 , G06F11/073 , G06F11/0751 , G06F12/0246 , G06F2212/7202 , G11C29/76
摘要： A memory system comprises a nonvolatile memory comprising a memory block having multiple pages, and a controller configured to control the nonvolatile memory to store data in the memory block according to a command and logical address received from an external source. The controller is configured to determine whether the logical address is currently mapped to a bad page of the memory block by referring to a bad page map, and as a consequence of determining that the logical address corresponds to the bad page, remaps the logical address to a different page and stores dummy data in the bad page.
摘要翻译： 存储器系统包括非易失性存储器，其包括具有多个页面的存储块，以及控制器，被配置为根据从外部源接收的命令和逻辑地址来控制非易失性存储器将数据存储在存储块中。 控制器被配置为通过参考坏页映射来确定逻辑地址当前是否被映射到存储器块的坏页，并且作为确定逻辑地址对应于坏页的结果，将逻辑地址重新映射到 不同的页面，并将虚拟数据存储在坏页面中。
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