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    SEMICONDUCTOR MEMORY DEVICE
    1.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20240334677A1

    公开(公告)日：2024-10-03

    申请号：US18480389

    申请日：2023-10-03

    申请人： Samsung Electronics Co., Ltd.

    发明人： Sangho LEE ,  Moonyoung JEONG ,  Ilgweon KIM ,  Yoongi HONG

    IPC分类号： H10B12/00

    CPC分类号： H10B12/315 ,  H10B12/05

    摘要： A semiconductor memory device includes a bit line, first and second word lines spaced apart from each other on the bit line, a back gate electrode between the first and second word lines, a first active pattern between the first word line and the back gate electrode, a second active pattern between the second word line and the back gate electrode, contact patterns connected to the first and second active patterns, respectively, and a first gate insulating pattern between the first active pattern and the first word line and between the second active pattern and the second word line. A top surface of the first gate insulating pattern is located at substantially a same height as top surfaces of the first and second word lines. The first gate insulating pattern includes a high-k dielectric material.

    SEMICONDUCTOR MEMORY DEVICE
    2.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20220352170A1

    公开(公告)日：2022-11-03

    申请号：US17725069

    申请日：2022-04-20

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Kyunghwan LEE ,  Yongseok KIM ,  Ilgweon KIM ,  Hyeoungwon SEO ,  Sungwon YOO ,  Jaeho HONG

    IPC分类号： H01L27/108

    摘要： A semiconductor memory device includes a word line extending in a vertical direction, a semiconductor pattern having a ring-shaped horizontal cross-section that extends around the word line, a bit line disposed at a first end of the semiconductor pattern, and a capacitor structure disposed at second end of the semiconductor pattern. The capacitor structure includes a lower electrode layer electrically connected to the second end of the semiconductor pattern, having a ring-shaped horizontal cross-section, and including a connector extending in the vertical direction. A first segment extends in a horizontal direction from an upper end of the connector, and a second segment extends in the horizontal direction from a lower end of the connector. An upper electrode layer surrounded by the lower electrode layer, extends in the vertical direction, and a capacitor dielectric layer is between the lower electrode layer and the upper electrode layer.

    SEMICONDUCTOR MEMORY DEVICE
    3.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20220216239A1

    公开(公告)日：2022-07-07

    申请号：US17503713

    申请日：2021-10-18

    申请人： Samsung Electronics Co., Ltd.

    发明人： Sungwon YOO ,  Yongseok KIM ,  Ilgweon KIM ,  Hyuncheol KIM ,  Hyeoungwon SEO ,  Kyunghwan LEE ,  Jaeho HONG

    IPC分类号： H01L27/12 ,  H01L27/13 ,  H01L25/065 ,  H01L25/18 ,  H01L21/84

    摘要： A semiconductor memory device is disclosed. The semiconductor memory device may include a data storage layer including data storage devices, an interconnection layer disposed on the data storage layer, and a selection element layer provided between the data storage layer and the interconnection layer. The interconnection layer may include bit lines extending in a first direction. The selection element layer may include a cell transistor connected between one of the data storage devices and one of the bit lines, and the cell transistor may include an active pattern and a word line, which crosses the active pattern and is extended in a second direction crossing the first direction.

    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    4.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20160079246A1

    公开(公告)日：2016-03-17

    申请号：US14849651

    申请日：2015-09-10

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Ji Hun KIM ,  Ilgweon KIM ,  Junhwa SONG ,  Jeonghoon OH ,  WonSeok YOO ,  Eun-Sun LEE

    IPC分类号： H01L27/108 ,  H01L21/311 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/768 ,  H01L49/02 ,  H01L29/06 ,  H01L21/306 ,  H01L21/762 ,  H01L21/02

    CPC分类号： H01L27/10894 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823807 ,  H01L27/10805 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/1085 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10891 ,  H01L28/91

    摘要： A method of fabricating a semiconductor device, the method including etching a portion of a substrate including a first region and a second region to form a device isolation trench; forming a device isolation layer defining active regions by sequentially stacking a first insulating layer, a second insulating layer, and a third insulating layer on an inner surface of the device isolation trench; forming word lines buried in the substrate of the first region, the word lines extending in a first direction to intersect the active region of the first region, the word lines being spaced apart from each other; forming a first mask layer covering the word lines on the substrate of the first region, the first mask layer exposing the substrate of the second region; forming a channel layer on the substrate of the second region; and forming a gate electrode on the channel layer.

    摘要翻译： 一种制造半导体器件的方法，所述方法包括蚀刻包括第一区域和第二区域的衬底的一部分以形成器件隔离沟槽; 通过在器件隔离沟槽的内表面上依次层叠第一绝缘层，第二绝缘层和第三绝缘层，形成限定有源区的器件隔离层; 形成掩埋在第一区域的衬底中的字线，字线在第一方向上延伸以与第一区域的有源区相交，字线彼此间隔开; 形成覆盖第一区域的衬底上的字线的第一掩模层，第一掩模层暴露第二区域的衬底; 在所述第二区域的衬底上形成沟道层; 以及在沟道层上形成栅电极。

    SEMICONDUCTOR DEVICES
    5.
    发明申请
    SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20220199793A1

    公开(公告)日：2022-06-23

    申请号：US17443553

    申请日：2021-07-27

    申请人： Samsung Electronics Co., Ltd.

    发明人： Hyuncheol KIM ,  Yongseok KIM ,  Ilgweon KIM ,  Seokhan PARK ,  Kyunghwan LEE ,  Jaeho HONG

    IPC分类号： H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L23/482

    摘要： A semiconductor device includes a plurality of semiconductor structures disposed on a substrate, a first conductive pattern, a first conductive pattern, a gate insulation pattern, a second conductive pattern and a second impurity region. Each of the semiconductor structures includes a first semiconductor pattern that has a linear shape that extends in a first direction and second semiconductor patterns that protrude from an upper surface of the first semiconductor pattern in a vertical direction. The semiconductor structures are spaced apart from each other in a second direction perpendicular to the first direction. The first conductive pattern is formed between the first semiconductor patterns. The first impurity region is formed in an opening in the first semiconductor pattern adjacent to a first sidewall of the second semiconductor pattern. The first impurity region includes an impurity diffusion harrier pattern and a polysilicon pattern doped with impurities

    INTEGRATED CIRCUIT DEVICES
    6.
    发明申请
    INTEGRATED CIRCUIT DEVICES 有权

    公开(公告)号：US20220076732A1

    公开(公告)日：2022-03-10

    申请号：US17245334

    申请日：2021-04-30

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Taesung KANG ,  Youngkyu LEE ,  Kyoungmin KIM ,  Ilgweon KIM ,  Bokyeon WON ,  Seokjae LEE ,  Sungho JANG ,  Joon HAN

    IPC分类号： G11C11/4091 ,  H01L27/108

    摘要： An integrated circuit device includes a sense amplifier configured to sense a voltage change of a bit line, wherein the sense amplifier includes: a sense amplifier unit connected to the bit line and a complementary bit line, configured to sense the voltage change of the bit line in response to a control signal, configured to adjust voltages of a sensing bit line and a complementary sensing bit line based on the sensed voltage change, and including a first PMOS transistor and a first NMOS transistor; and a first offset canceling unit connecting the bit line to the complementary sensing bit line in response to an offset canceling signal, and including a first offset canceling transistor arranged between the first NMOS transistor and the first PMOS transistor, wherein the first offset canceling transistor shares a common impurity region with the first NMOS transistor.