公开(公告)号：US20240259007A1

公开(公告)日：2024-08-01

申请号：US18428045

申请日：2024-01-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwanyeob CHAE ,  Chulwoo KIM ,  Yoonjae CHOI ,  Kyeongkeun KANG

IPC: H03K7/02 ,  G06F13/16 ,  G11C11/4076 ,  H03K3/037 ,  H03K19/20

CPC classification number: H03K7/02 ,  G11C11/4076 ,  H03K3/037 ,  H03K19/20 ,  G06F13/1668

Abstract: A 4-level pulse amplitude modulation (PAM-4) decoder including: a comparator configured to receive first input data, second input data, and a clock signal and output first comparison data and second comparison data, wherein the first comparison data and the second comparison data are comparison results for the first input data and the second input data; a clock delay circuit configured to delay the clock signal and generate a delayed clock signal; and a time-windowed least significant bit (LSB) decoder configured to receive the first comparison data, the second comparison data, and the delayed clock signal, wherein the time-windowed LSB decoder is configured to perform a decoding when the delayed clock signal is at a first level.

公开(公告)号：US20230344417A1

公开(公告)日：2023-10-26

申请号：US18087439

申请日：2022-12-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwanyeob CHAE ,  Chulwoo KIM ,  Yoonjae CHOI ,  Kyeongkeun KANG

IPC: H03K17/687 ,  H03K3/012

CPC classification number: H03K3/012 ,  H03K17/6872

Abstract: A semiconductor device is provided. The semiconductor device includes: an equalizer circuit configured to output a first control signal corresponding to a first bit of original two-bit data and a second control signal corresponding to a second bit of the original two-bit data; and a driver circuit including a plurality of pull-up transistors connected between an output node and a first power node configured to provide a first power supply voltage, and a plurality of pull-down transistors connected between the output node and a second power node configured to provide a second power supply voltage, wherein the second power supply voltage is lower than the first power supply voltage, and the driver circuit is connected to the equalizer circuit in series. The plurality of pull-up transistors includes a first pull-up transistor and a second pull-up transistor connected to each other in parallel, between the first power node and the output node, and a third pull-up transistor and a fourth pull-up transistor connected to each other in series, between the first power node and the output node.