公开(公告)号：US20200273507A1

公开(公告)日：2020-08-27

申请号：US16871096

申请日：2020-05-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwanyeob CHAE ,  Sanghune PARK

IPC: G11C7/22 ,  G06F13/16

Abstract: A read margin control circuit is provided. The read margin control circuit includes a delay circuit that delays a data input/output signal and generates delay signals having different phases from each other, a sampler that samples the delay signals based on a data strobe signal to generate sampling values, and a determiner configured to determine a data valid window of the data input/output signal based on the sampling values.

公开(公告)号：US20240259007A1

公开(公告)日：2024-08-01

申请号：US18428045

申请日：2024-01-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwanyeob CHAE ,  Chulwoo KIM ,  Yoonjae CHOI ,  Kyeongkeun KANG

IPC: H03K7/02 ,  G06F13/16 ,  G11C11/4076 ,  H03K3/037 ,  H03K19/20

CPC classification number: H03K7/02 ,  G11C11/4076 ,  H03K3/037 ,  H03K19/20 ,  G06F13/1668

Abstract: A 4-level pulse amplitude modulation (PAM-4) decoder including: a comparator configured to receive first input data, second input data, and a clock signal and output first comparison data and second comparison data, wherein the first comparison data and the second comparison data are comparison results for the first input data and the second input data; a clock delay circuit configured to delay the clock signal and generate a delayed clock signal; and a time-windowed least significant bit (LSB) decoder configured to receive the first comparison data, the second comparison data, and the delayed clock signal, wherein the time-windowed LSB decoder is configured to perform a decoding when the delayed clock signal is at a first level.

公开(公告)号：US20230344417A1

公开(公告)日：2023-10-26

申请号：US18087439

申请日：2022-12-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwanyeob CHAE ,  Chulwoo KIM ,  Yoonjae CHOI ,  Kyeongkeun KANG

IPC: H03K17/687 ,  H03K3/012

CPC classification number: H03K3/012 ,  H03K17/6872

Abstract: A semiconductor device is provided. The semiconductor device includes: an equalizer circuit configured to output a first control signal corresponding to a first bit of original two-bit data and a second control signal corresponding to a second bit of the original two-bit data; and a driver circuit including a plurality of pull-up transistors connected between an output node and a first power node configured to provide a first power supply voltage, and a plurality of pull-down transistors connected between the output node and a second power node configured to provide a second power supply voltage, wherein the second power supply voltage is lower than the first power supply voltage, and the driver circuit is connected to the equalizer circuit in series. The plurality of pull-up transistors includes a first pull-up transistor and a second pull-up transistor connected to each other in parallel, between the first power node and the output node, and a third pull-up transistor and a fourth pull-up transistor connected to each other in series, between the first power node and the output node.

公开(公告)号：US20190214063A1

公开(公告)日：2019-07-11

申请号：US16211777

申请日：2018-12-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwanyeob CHAE ,  Hyungkweon LEE

IPC: G11C7/22 ,  G06F13/16

Abstract: An electronic circuit including: a first delay line circuit to generate a first data strobe by delaying a second data strobe, such that an edge of the first data strobe is aligned within a first time interval; and a sampling circuit to sample the first data signal at the edge of the first data strobe, wherein plural data signals include the first data signal and a second data signal, wherein timings of the plural data signals deviate from a reference timing of a reference data strobe by plural time lengths, wherein the first data signal deviates from the reference timing by a first time length of the plural time lengths, and wherein an edge of the second data strobe is aligned within a second time interval, wherein a timing of the second data signal deviates from the reference timing by a shortest time length of the plural time lengths.

公开(公告)号：US20190214062A1

公开(公告)日：2019-07-11

申请号：US16118863

申请日：2018-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwanyeob CHAE ,  Sanghune PARK

IPC: G11C7/22 ,  G06F13/16

Abstract: A read margin control circuit is provided. The read margin control circuit includes a delay circuit that delays a data input/output signal and generates delay signals having different phases from each other, a sampler that samples the delay signals based on a data strobe signal to generate sampling values, and a determiner configured to determine a data valid window of the data input/output signal based on the sampling values.

公开(公告)号：US20170098624A1

公开(公告)日：2017-04-06

申请号：US15277339

申请日：2016-09-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwanyeob CHAE ,  Sanghoon JOO ,  Jong-Ryun CHOI ,  Jin-Ho CHOI

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/58

CPC classification number: H01L25/0657 ,  H01L23/50 ,  H01L23/5221 ,  H01L23/5286 ,  H01L23/585 ,  H01L23/60 ,  H01L24/02 ,  H01L24/05 ,  H01L24/06 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/0233 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/02377 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/06131 ,  H01L2224/06135 ,  H01L2224/14131 ,  H01L2224/14135 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06555 ,  H01L2924/00012

Abstract: A semiconductor chip including a plurality of input/output units includes: a plurality of additional pads disposed on a surface of the semiconductor chip, wherein the plurality of additional pads include at least one of a first additional pad to which a ground voltage is applied and a second additional pad to which a power supply voltage is applied; and a plurality of pads disposed on the surface of the semiconductor chip, wherein the plurality of pads include at least one of a first pad to which the ground voltage is applied and a second pad to which the power supply voltage is applied, and further include a third pad through which a signal is input and/or output. The at least one of the first additional pad and the second additional pad is disposed on an input/output unit where the third pad is disposed, among the plurality of input/output units.