公开(公告)号：US20240021615A1

公开(公告)日：2024-01-18

申请号：US18163573

申请日：2023-02-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoonjeong KIM ,  Yeongmin JEON ,  Hyewon JANG

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/092 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/775 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66545 ,  H01L29/66439

Abstract: A semiconductor device having active regions including a first active region and a second active region parallel to each other and respectively extending on a substrate in a first horizontal direction, a field region defining the active regions, a first insulating structure extending in the first horizontal direction on the field region, a gate structure extending, in a second horizontal direction, to intersect the active regions and the first insulating structure, source/drain regions disposed on at least one side of the gate structure, the source/drain regions including first source/drain regions on the first active region and second source/drain regions on the second active region, and a common contact plug on a first side of the gate structure and connected to the first and second source/drain regions opposing each other. The first insulating structure includes a first portion overlapping the gate structure in a vertical direction.

公开(公告)号：US20220384415A1

公开(公告)日：2022-12-01

申请号：US17527432

申请日：2021-11-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Panjae PARK ,  Byungju KANG ,  Yoonjeong KIM ,  Kwanyoung CHUN

IPC: H01L27/02 ,  H01L27/092 ,  H01L27/118 ,  H01L29/08

Abstract: An integrated circuit chip including a substrate including first and second element regions; a first channel active region extending in a first direction; a second channel active region; gate lines extending in a second direction and intersecting the first and second channel active regions; a diffusion break extending in the second direction; source/drain regions at opposite sides of the gate lines and on the first and second channel active regions; a first power line electrically connected to the source/drain regions; and a second power line electrically connected to the source/drain regions and having a lower voltage level than the first power line, wherein the diffusion break includes a first region including an insulator and overlapping the first element region, and a second region including a same material as the gate lines and overlapping the second element region, wherein the second region is electrically connected to the second power line.